mpc9993 Integrated Device Technology, mpc9993 Datasheet

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mpc9993

Manufacturer Part Number
mpc9993
Description
Redundant Lvpecl 2 1 Dymic Clock Switch
Manufacturer
Integrated Device Technology
Datasheet

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Part Number:
mpc9993AC
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
mpc9993ACR2
Manufacturer:
IDT, Integrated Device Technology Inc
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10 000
Part Number:
mpc9993FA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
IDT™ Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Intelligent Dynamic Clock Switch
(IDCS) PLL Clock Driver
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Intelligent Dynamic Clock Switch
(IDCS) PLL Clock Driver
tree designs. The device receives two differential LVPECL clock signals from
which it generates 5 new differential LVPECL clock outputs. Two of the output
pairs regenerate the input signals frequency and phase while the other three
pairs generate 2x, phase aligned clock outputs.
Features
Functional Description
monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or
LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that
CLK is the primary clock, the IDCS will switch to the good secondary clock and
phase/frequency alignment will occur with minimal output phase disturbance.
The typical phase bump caused by a failed clock is eliminated. (See Application
Information section).
The MPC9993 is a PLL clock driver designed specifically for redundant clock
The MPC9993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously
32-Lead Pb-Free Package Available
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control I/O
3.3 V Operation
32-Lead LQFP Packaging
Man_Override
Clk_Selected
Alarm_Reset
Inp1bad
Inp0bad
PLL_En
Sel_Clk
Ext_FB
Ext_FB
CLK0
CLK0
CLK1
CLK1
Dynamic
Switch
Logic
MR
OR
Figure 1. Block Diagram
800 – 1600 MHz
PLL
1
÷16
÷8
INTELLIGENT DYNAMIC
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
PLL CLOCK DRIVER
Pb-FREE PACKAGE
MPC9993
CLOCK SWITCH
CASE 873A-04
CASE 873A-04
FA SUFFIX
AC SUFFIX
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
DATA SHEET
Rev 3, 06/2005
MPC9993
MPC9993
MPC9993

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mpc9993 Summary of contents

Page 1

... Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs ...

Page 2

... Q outputs LOW. Asynchronous to the clock (50 kΩ pullup) PLL power supply Digital power supply PLL ground Digital ground Inp0bad 14 Inp1bad 13 Clk_Selected 12 GND 11 Ext_FB 10 Ext_FB 9 GND 8 Pin Definition Advanced Clock Drivers Device Data Freescale Semiconductor NETCOM MPC9993 ...

Page 3

... AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MPC9993 to be used in applications requiring industrial temperature range recommended that users of the MPC9993 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. IDT™ ...

Page 4

... – 0. 1.3 V Differential operation V –0.3 V Differential operation CC ±100 μ GND IN CC Termination 50 Ω –0. Termination 50 Ω –1. 180 mA GND Pins Pin CC_PLL (DC) CMR Advanced Clock Drivers Device Data Freescale Semiconductor MPC9993 ...

Page 5

... PLL locked 200 MHz 75 % +2.0 ns PLL_EN=1 1.8 ns PLL_EN 200 400 ps 100 200 0.70 ns 20% to 80% ÷ FB ref VCO (AC) CMR (AC) impacts the SPO, device and part-to-part PP ° ). Delta period change per MPC9993 MPC9993 5 ...

Page 6

... Hot insertion and withdrawal In PECL applications, a powered up driver will experience a low impedance path through an MPC9993 input to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input signals ...

Page 7

... IDT™ Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE 7 NETCOM PAGE MPC9993 MPC9993 7 ...

Page 8

... IDT™ Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver MPC9993 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 8 PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE Advanced Clock Drivers Device Data 8 NETCOM PAGE MPC9993 Freescale Semiconductor ...

Page 9

... IDT™ Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE 9 NETCOM PAGE MPC9993 MPC9993 9 ...

Page 10

... MPC9448 MC88915 MPC9993 MPC92459 PART NUMBERS Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver 900 MHz Low Voltage LVDS Clock Synthesizer 3.3 V/2.5 V LVCMOS 1:12 Clock Fanout Buffer Low Skew CMOS PLL Clock Drivers INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www ...

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