mpc9992 Integrated Device Technology, mpc9992 Datasheet

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mpc9992

Manufacturer Part Number
mpc9992
Description
3.3v Differential Lvpecl Pll Clock Generator
Manufacturer
Integrated Device Technology
Datasheet

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IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
3.3 V Differential ECL/PECL PLL
Clock Generator
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V Differential ECL/PECL PLL
Clock Generator
SiGe technology and a fully differential design ensures optimum skew and PLL
jitter performance. The performance of the MPC9992 makes the device ideal for
workstation, mainframe computer and telecommunication applications. With
output frequencies up to 400 MHz and output skews less than 100 ps the device
meets the needs of the most demanding clock applications. The MPC9992 offers
a differential PECL input and a crystal oscillator interface. All control signals are
LVCMOS compatible.
Features
Functional Description
quency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency
range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input
relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback fre-
quency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input ref-
erence frequency range.
erator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between
output frequencies.
nal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input
reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock
frequency specification and all other PLL characteristics do not apply.
Assertion of the reset signal forces all outputs to the logic low state.
PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels
with the capability to drive terminated 50 Ω transmission lines.
The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using
The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock fre-
The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC gen-
The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock sig-
The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted.
The MPC9992 is fully 3.3 V compatible and requires no external loop filter components. The differential clock input (PCLK) is
The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package.
7 differential outputs, PLL based clock generator
SiGe technology supports minimum output skew (max. 100 ps)
Supports up to two generated output clock frequencies with a maximum clock
frequency up to 400 MHz
Selectable crystal oscillator interface and PECL compatible clock input
SYNC pulse generation
PECL compatible differential clock inputs and outputs
Single 3.3 V (PECL) supply
Ambient temperature range 0°C to +70°C
Standard 32 lead LQFP package
Pin and function compatible to the MPC992
32-lead Pb-free Package Available
1
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
CLOCK GENERATOR
3.3 V DIFFERENTIAL
Pb-FREE PACKAGE
MPC9992
CASE 873A-04
CASE 873A-04
ECL/PECL
FA SUFFIX
AC SUFFIX
DATA SHEET
Rev 5, 06/2005
MPC9992
MPC9992
MPC9992

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mpc9992 Summary of contents

Page 1

... Assertion of the reset signal forces all outputs to the logic low state. The MPC9992 is fully 3.3 V compatible and requires no external loop filter components. The differential clock input (PCLK) is PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the capability to drive terminated 50 Ω ...

Page 2

... QA0 28 QA0 MPC9992 29 GND 30 V CC_PLL Figure 2. MPC9992 32-Lead Package Pinout (Top View) 2 Bank A QA0 QA0 QA1 QA1 ÷2, ÷4 QA2 ÷4, ÷6, ÷10 QA2 QA3 ÷16, ÷24, ÷40 QA3 Sync Pulse Bank B QB0 QB0 QB1 ...

Page 3

... Selects VCO÷2. The VCO frequency is scaled by a factor of 2 (high input frequency range) PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC9992 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. MR/STOP 0 Normal operation VCO_SEL and FSEL[1:0] control the operating PLL frequency range and input/output frequency ratios ...

Page 4

... AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MPC9992 to be used in applications requiring industrial temperature range recommended that users of the MPC9992 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application ...

Page 5

... V -0.3 V Differential operation CC ±120 µ GND 0.3 V LVCMOS CC 0.8 V LVCMOS ±120 µ GND –0.880 – –1.620 – pin CC CC_PLL pin CC_PLL 110 mA GND pins (DC) CMR MPC9992 MPC9992 5 ...

Page 6

... AC characteristics apply for parallel output termination of 50 Ω bypass mode, the MPC9992 divides the input reference clock. 3. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: ÷ (M ⋅ VCO_SEL) and 10 MHz ≤ f ...

Page 7

... SYNC Output Description The MPC9992 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9992 monitors the relationship between the A bank and Qa Qb QSYNC Qa ...

Page 8

... MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator Power Supply Filtering The MPC9992 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the V power supply impacts the device CC_PLL characteristics, for instance I/O jitter. The MPC9992 provides ...

Page 9

... V Differential ECL/PECL PLL Clock Generator IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE 9 NETCOM PAGE MPC9992 MPC9992 9 ...

Page 10

... V Differential ECL/PECL PLL Clock Generator MPC9992 IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 10 PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE Advanced Clock Drivers Device Data 10 NETCOM PAGE MPC9992 Freescale Semiconductor ...

Page 11

... V Differential ECL/PECL PLL Clock Generator IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE 11 NETCOM PAGE MPC9992 MPC9992 11 ...

Page 12

... MPC92459 MPC9992 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer 3.3 V Differential ECL/PECL PLL Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. ...

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