mpc9992 Integrated Device Technology, mpc9992 Datasheet
mpc9992
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mpc9992 Summary of contents
Page 1
... Assertion of the reset signal forces all outputs to the logic low state. The MPC9992 is fully 3.3 V compatible and requires no external loop filter components. The differential clock input (PCLK) is PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the capability to drive terminated 50 Ω ...
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... QA0 28 QA0 MPC9992 29 GND 30 V CC_PLL Figure 2. MPC9992 32-Lead Package Pinout (Top View) 2 Bank A QA0 QA0 QA1 QA1 ÷2, ÷4 QA2 ÷4, ÷6, ÷10 QA2 QA3 ÷16, ÷24, ÷40 QA3 Sync Pulse Bank B QB0 QB0 QB1 ...
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... Selects VCO÷2. The VCO frequency is scaled by a factor of 2 (high input frequency range) PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC9992 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. MR/STOP 0 Normal operation VCO_SEL and FSEL[1:0] control the operating PLL frequency range and input/output frequency ratios ...
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... AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MPC9992 to be used in applications requiring industrial temperature range recommended that users of the MPC9992 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application ...
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... V -0.3 V Differential operation CC ±120 µ GND 0.3 V LVCMOS CC 0.8 V LVCMOS ±120 µ GND –0.880 – –1.620 – pin CC CC_PLL pin CC_PLL 110 mA GND pins (DC) CMR MPC9992 MPC9992 5 ...
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... AC characteristics apply for parallel output termination of 50 Ω bypass mode, the MPC9992 divides the input reference clock. 3. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: ÷ (M ⋅ VCO_SEL) and 10 MHz ≤ f ...
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... SYNC Output Description The MPC9992 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9992 monitors the relationship between the A bank and Qa Qb QSYNC Qa ...
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... MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator Power Supply Filtering The MPC9992 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the V power supply impacts the device CC_PLL characteristics, for instance I/O jitter. The MPC9992 provides ...
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... V Differential ECL/PECL PLL Clock Generator IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE 9 NETCOM PAGE MPC9992 MPC9992 9 ...
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... V Differential ECL/PECL PLL Clock Generator MPC9992 IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 10 PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE Advanced Clock Drivers Device Data 10 NETCOM PAGE MPC9992 Freescale Semiconductor ...
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... V Differential ECL/PECL PLL Clock Generator IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE 11 NETCOM PAGE MPC9992 MPC9992 11 ...
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... MPC92459 MPC9992 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer 3.3 V Differential ECL/PECL PLL Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. ...