mpc9992 Integrated Device Technology, mpc9992 Datasheet - Page 6

• Manufacturer Part Number: mpc9992
• Description: 3.3v Differential Lvpecl Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9992
3.3 V Differential ECL/PECL PLL Clock Generator
6
Table 7. AC Characteristics (V
MPC9992
10. See application section for a jitter calculation for other confidence factors than 1 σ.
11. –3 dB point of PLL transfer characteristics.
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. In bypass mode, the MPC9992 divides the input reference clock.
3. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
5. V
6. V
7. Calculation of reference duty cycle limits: DC
8. Output duty cycle for QAx and QBx outputs. The pulse width for the QSYNC output is equal to one QAx output period t
9. Jitter data is valid f
Symbol
t
V
t
t
JIT(PER)
f
range and the input swing lies within the V
the input duty cycle range is 10% < DC < 90%.
PW,MIN
V
JIT(CC)
t
t
XTAL(min, max)
f
t
f
f
JIT(∅)
O(P-P)
LOCK
XTAL
V
sk(O)
BW
t
PP
CMR
VCO
MAX
DC
f
CMR
r
ref
, t
PP
f
is the minimum differential input voltage swing required to maintain AC characteristics.
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input Reference Frequency
Input Reference Frequency in PLL Bypass Mode
Crystal Interface Frequency Range
VCO Frequency Range
Output Frequency
Differential Input Voltage
Differential Input Crosspoint Voltage
Differential Output Voltage (peak-to-peak)
Input Reference Pulse Width
Output-to-Output Skew
Output Duty Cycle
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
PLL Closed Loop Bandwidth
Maximum PLL Lock Time
Output Rise/Fall Time
= f
VCO(min, max)
ref
= 25 MHz.
(9)
(9)
Characteristics
÷ (M ⋅ VCO_SEL) and 10 MHz ≤ f
(8)
CC
(9)
(4)
= 3.3 V ± 5%, GND = 0 V, T
(5)
(peak-to-peak)
(11)
(7)
PP
REF,MIN
(AC) specification.
(3)
(6)
÷160 feedback
÷160 feedback
÷32 feedback
÷48 feedback
÷64 feedback
÷80 feedback
÷96 feedback
RMS (1 σ)
÷32 feedback
÷48 feedback
÷64 feedback
÷80 feedback
÷96 feedback
= t
÷12 output
÷16 output
÷20 output
÷24 output
÷48 output
÷4 output
÷8 output
PW,MIN
(PCLK)
(PCLK)
(2)
(10)
⋅ f
XTAL
REF
A
TT
6
≤ 20 MHz.
= 0°C to +70°C)
⋅ 100% and DC
.
16.67
200.0
100.0
25.0
12.5
10.0
8.33
66.6
50.0
40.0
33.3
16.6
0.05
Min
800
5.0
0.3
1.2
0.6
2.0
10
48
0.60-1.5
0.40-1.2
0.30-1.0
0.30-0.8
0.20-0.7
0.15-0.4
REF,MAX
Typ
0.8
50
30
43
86
(1)
= 100% – DC
Advanced Clock Drivers Device Data
V
16.67
400.0
200.0
133.3
100.0
CC
1600
Max
50.0
33.3
25.0
20.0
10.0
80.0
66.6
33.3
400
100
106
212
1.3
1.0
20
52
79
10
–0.3
ref
REF, MIN.
= f
Freescale Semiconductor
VCO
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ms
ns
ps
ps
ps
ps
ns
%
V
V
V
E.g. at f
÷ (M ⋅ VCO_SEL)
QA
PLL locked
PLL bypass
PLL locked
20% to 80%
± 5%.
REF
Condition
CMR
= 50 MHz
(AC)
NETCOM
MPC9992