vsc880 Vitesse Semiconductor Corp, vsc880 Datasheet
vsc880
Available stocks
Related parts for vsc880
vsc880 Summary of contents
Page 1
... Cell Mode • Multicast Supported in All Modes VSC880 Block Diagram ...
Page 2
... Serial Crosspoint Switch General Description The VSC880 is a 16x16 serial crosspoint switch with serial data rates at 2.125Gb/s. The VSC880 has been designed to operate with the VSC870 backplane transceiver to establish a synchronous high performance switching system with an aggregate bandwidth of 32Gb/s. The switch chip transmits the master word clock (62.5Mb/s), and master cell clock (if used) to all port cards through the serial data channels ...
Page 3
... Data Sheet VSC880 Pin Name RESYNEN Resynch Enable INT Interrupt MEN Reserved FACLPBK Facility Loop Back CMODE Cell Mode TESTEN Scan Test Enable SCANIN Scan Data In SCANOUT Scan Data Out WCLK Word Clock REFCLK Reference Clock TCLKEN Test Clock Enable CCLK ...
Page 4
... Core Power Supply Functional Description The VSC880 switch can be used in conjunction with the VSC870 transceivers to support two modes of operation: Packet Mode and Cell Mode. In Packet mode, the chip set provides a switching system to support variable length, self-routing data packets. In Cell Mode, the chip set provides a cell synchronous switching system with a user defined scheduler ...
Page 5
... Data Sheet VSC880 1.1.2 Data Scrambling To allow the VSC870 CRU to recover the bit clock, a 15% edge transition density must be guaranteed on the serial data links. All command words and connection request words contain this required density. In order to get this density on data words, scrambling must be employed by the transceiver (see VSC870 data sheet). ...
Page 6
... --------------- Data Payload ---------------- 01=Flow control channel, Internet: www.vitesse.com Data Sheet VSC880 G52191-0, Rev 4.2 ...
Page 7
... Loopback The VSC880 supports a loopback function at the serial interfaces which is used in built-in self-test mode. If the BSTLPBK signal is set HIGH and TESTEN is set LOW, the serial transmit data is looped back to the serial receive side for all 16 channels. If the BSTLPBK signal is set HIGH and TESTEN is set HIGH, the serial transmit data is looped back to the serial receive side for channels 0-7 only ...
Page 8
... C1[3:0] C9[3:0] C2[3:0] C10[3:0] C3[3:0] C11[3:0] C4[3:0] C12[3:0] C5[3:0] C13[3:0] C6[3:0] C14[3:0] Internet: www.vitesse.com Data Sheet VSC880 Interrupt Status Register ITE ILE Interrupt Control Register BIST and Count Register CCLK error register LSB CCLK error register MSB DRU error register LSB DRU error register MSB Error threshold register LSB ...
Page 9
... Data Sheet VSC880 ADDR[5: ...
Page 10
... LPBK[15:0]Facility loopback register, bit 0 is channel 0 etc 1.5 Parallel CPU Interface There is a parallel 8 bit CPU interface on the VSC880 that can be used to read and write the status and control registers described above. This is an asynchronous interface that was design to operate with many common micro controllers that are available ...
Page 11
... Data Sheet VSC880 Figure 4: Switch Configuration Interface Functional Timing (CEN=0) REFCLK DATA[15:0] The switch configuration data for each port is as follows: F0[3:0] = FI[port9], FI[port8], FI[port1], FI[port0] F1[3:0] = FI[port11], FI[port10], FI[port3], FI[port2] F2[3:0] = FI[port13], FI[port12], FI[port5], FI[port4] F3[3:0] = FI[port15], FI[port14], FI[port7], FI[port6] C0[15:0] = Port9[3:0], Port8[3:0], Port1[3:0], Port0[3:0] ...
Page 12
... The BIST test can be run on no more than two ports at a time, for example: port 0 Page 12 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION < Internet: www.vitesse.com Data Sheet VSC880 port 3 port 8 port 0. G52191-0, Rev 4.2 01/05/01 ...
Page 13
... VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 G52191-0, Rev 4.2 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com 01/05/01 VITESSE SEMICONDUCTOR CORPORATION Figure 6: Packet Mode System Trans VSC870 Trans VSC870 Internet: www.vitesse.com High Performance 16x16 Serial Crosspoint Switch Switch Card Switch Chip VSC880 Page 13 ...
Page 14
... ------ Connection Bits ------ Internet: www.vitesse.com Data Sheet VSC880 ...
Page 15
... Data Sheet VSC880 Where: B[1:0]00=Undefined, 01=Flow control channel, 10=Flow control channel, 11=Acknowledge BRK1=This is the CRQ word for the next packet. This bit is used to break the current connection. M[0:15]Current outputs the transmitting channel is connected to D[3:0] User defined data sent by transmitting port card 2 ...
Page 16
... Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION Example 2: Start of Packet 11 Header BB 00 CRQ BB End of Packet BB 00 CRQ Zero or more IDLEs 00 IDLEs 11 Header BB Internet: www.vitesse.com Data Sheet VSC880 Start of Packet D0 CRQ D words before EOP D(N-D) DN End of Packet Zero or more IDLEs D0 G52191-0, Rev 4.2 01/05/01 ...
Page 17
... CRQ instead of the two normally received. 2.7 Flow Control Channel The VSC880 can support a back pressure mechanism by providing a flow control channel. The flow control channel is time shared with the signaling between the switch chip and the transceiver for acknowledgment and response bits. Therefore, it can only guarantee to pass the state information from input pin at the receiving port card through the switch and to the output pin at the transmitting port card ...
Page 18
... In Cell Mode (CMODE = HIGH), a more sophisticated arbitration scheme can be supported by using the VSC870 and the VSC880 switch in conjunction with a central (user defined) scheduler. In this mode, only fixed length data packets (cells) can be supported. A cell clock is connected to the switch chip, and the switch chip distributes the cell clock to all connected transceivers ...
Page 19
... Data Sheet VSC880 3.4 Transmitter Operation If CMODE is HIGH and the force IDLE register is set LOW, the transmitter sends data words from the switch fabric. If the force IDLE register is set HIGH, IDLE words are transmitted. At the end of the cell clock period, bits B[1:0] in all IDLE words are set embed the cell clock marker. For data words, user defined overhead bits are passed on to the destination as is ...
Page 20
... Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION Min Typ 2.5 2.5 100 100 T REFCLK T INSU Description T T INT INT Internet: www.vitesse.com Data Sheet VSC880 Max Units Conditions 10-90% @ 50pF ns ns 10-90% @ 50pF ps 20-80% 20-80 INH Min Typ Max Units 16 ns ...
Page 21
... Data Sheet VSC880 Table 3: Receive Data Output Timing Table Parameter T Interrupt pulse width INT T RESET, RESYNEN pulse width RESET Figure 11: CPU Interface Write Cycle Timing T SU CWEN CSEL ADDR[5:0] CDATA[7: Figure 12: CPU Interface Read Cycle Timing T SU CWEN CSEL T A ADDR[5:0] ...
Page 22
... DD DDA DD DDA (V = 3.3V + 5%) DDA DDA (V DDX (V = 2. 3.3V+5 2.5V+5%, all quadrants powered 3.3V+5 2.0V+5%, all quadrants powered Internet: www.vitesse.com Data Sheet VSC880 Max Units Conditions — - Min V OUT 1000 mV 100 across input 2 Min V IN 1600 mV — ...
Page 23
... Data Sheet VSC880 Absolute Maximum Ratings Power Supply Voltage (V ) Potential to GND.................................................................................-0.5V to +4V DD Power Supply Voltage (V ) Potential to GND ................................................................................-0. Input Voltage (LVDS inputs) .......................................................................................... -0. Input Voltage (TTL inputs) ......................................................................................................... -0.5V to 5.5V DC Input Voltage (TTL inputs for CDATA[7:0]).................................................................. -0. Output Voltage (TTL outputs) ........................................................................................ -0. Output Current (TTL outputs) .................................................................................................................. +/-50mA Output Current (LVDS outputs) ...
Page 24
... TXS[15]- NC C23 VDD4 VMM D01 RXS[15]+ NC D02 VSS VDD1 D03 TXS[1]+ NC D04 VSS VSSA D05 RXS[1]- Internet: www.vitesse.com Data Sheet VSC880 Pin Signal Pin D06 VDD1 G04 D07 VDD4 G20 D08 RXS[14]- G21 D09 VSS G22 D10 TXS[14]+ G23 D11 VDD1 ...
Page 25
... Data Sheet VSC880 Signal Pin VMM M01 RXS[10]- VDD1 M02 TXS[3]- M03 TXS[6]- TXS[3]+ M04 TXS[12]+ M20 RXS[6]+ TXS[12]- M21 RXS[9]+ VDD4 M22 VMM M23 TXS[9]- VMM N01 VDD2 N02 TXS[6]+ TXS[4]- N03 TXS[4]+ N04 RXS[6]- TXS[11]+ N20 TXS[11]- N21 VDD3 ...
Page 26
... High Performance 16x16 Serial Crosspoint Switch Package Information Page 26 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION 304 BGA Package Internet: www.vitesse.com Data Sheet VSC880 G52191-0, Rev 4.2 01/05/01 ...
Page 27
... With natural convection, the junction to case thermal o resistance is estimated to be 0.45 Table 12.3. Note: The VSC880 is not guaranteed to operate under cold start conditions. If the ambient temperature seconds after power is applied, the case temperature will be at least 30 equilibrium and ready for operation ...
Page 28
... High Performance 16x16 Serial Crosspoint Switch Page 28 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION This page left intentionally blank. Internet: www.vitesse.com Data Sheet VSC880 G52191-0, Rev 4.2 01/05/01 ...