mc10ep196 ON Semiconductor, mc10ep196 Datasheet - Page 11

• Manufacturer Part Number: mc10ep196
• Description: 3.3v/5vecl Programmable Delay Chip With Ftune
• Manufacturer: ON Semiconductor

Cascading Multiple EP196s
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP196s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E196.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range; however, this
increase is at the expense of a longer minimum delay.
pictured in Figure 7. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D10
of chip #1 in Figure 6 is low, the cascade output will also be
low while the cascade bar output will be a logical high. In
this condition, the SETMIN pin of chip #2 will be asserted
and thus all of the latches of chip #2 will be reset and the
device will be set at its minimum delay.
SETMAX deasserted so that its delay will be controlled
entirely by the address bus A0–A9. If the delay needed is
greater than can be achieved with 1023 gate delays
(1111111111 on the A0–A9 address bus), D10 will be
asserted to signal the need to cascade the delay to the next
EP196 device. When D10 is asserted, the SETMIN pin of
INPUT
To increase the programmable range of the EP196,
An expansion of the latch section of the block diagram is
Chip #1, on the other hand, will have both SETMIN and
D8
D9
D10
IN
IN
V
V
V
BB
EF
CF
D7
Need if Chip #3 is used
D6
D5
CHIP #2
D4
EP196
V
EE
Figure 6. Cascading Interconnect Architecture
D3
MC10EP196, MC100EP196
D2
FTUNE
D1
V
V
V
V
D0
CC
CC
CC
EE
http://onsemi.com
Q
Q
11
two EP196s. As can be seen, this scheme can easily be
expanded for larger EP196 chains. The D10 input of the
EP196 is the cascade control pin. With the interconnect
scheme of Figure 6 when D10 is asserted, it signals the need
for a larger programmable range than is achievable with a
single device. The A11 address can be added to generate a
cascade output for the next EP196. For a 2–device
configuration, A11 is not required.
chip #2 will be deasserted and the SETMAX pin asserted,
resulting in the device delay to be the maximum delay.
Figure 8 shows the delay time of two EP196 chips in
cascade.
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 6. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
be used for additional delay and for finer resolution than 10
ps. As shown in Figure 5, an analog voltage input from DAC
can adjust the FTUNE pin with an extra 60 ps of delay for
each chip.
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Figure 6 illustrates the interconnect scheme for cascading
To expand this cascading scheme to more devices, one
Furthermore, to fully utilize EP196, the FTUNE pin can
D8
D9
D10
IN
IN
V
V
V
BB
EF
CF
D7
D6
D5
ADDRESS BUS
D4
CHIP #1
EP196
V
EE
D3
D2 D1
FTUNE
V
V
V
V
D0
CC
CC
CC
EE
Q
Q
DAC
OUTPUT