mc10ep196 ON Semiconductor, mc10ep196 Datasheet - Page 2

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mc10ep196

Manufacturer Part Number
mc10ep196
Description
3.3v/5vecl Programmable Delay Chip With Ftune
Manufacturer
ON Semiconductor
Datasheet
V
D1
D2
D3
D4
D5
D6
D7
EE
Warning: All V
to Power Supply to guarantee proper operation.
Figure 1. 32–Lead LQFP Pinout (Top View)
V
D8
EE
CC
D0 V
D9 D10
and V
EE
CC
MC100EP196
MC10EP196
pins must be externally connected
Q
IN
*
**
*** Short V
(V
EN
EN
LEN
LEN
SETMIN
SETMIN
SETMAX
SETMAX
V
V
V
SUPPLY
SUPPLY
POWER
IN
Q
CF
CF
CF
For TTL Mode, connect appropriate resistor between V
CC
Internal pulldown will provide logic low if pin left unconnected.
PECL
NECL
, V
V
V
CC
BB
EE
DATA INPUT OPERATING VOLTAGE TABLE
CF
)
V
V
CC
EF
Resistor Value
(pin 8) and V
MC10EP196, MC100EP196
FTUNE
V
1.5 kW
500 W
CMOS
CF
N/A
n
http://onsemi.com
No Connect
DATA SELECT INPUTS (D [0:10])
V
TRUTH TABLE
EF
EF
1.5 V
L*
L*
L*
L*
H
H
H
H
Pin***
(pin 7).
EN
CASCADE
CASCADE
V
SETMAX
SETMIN
LEN
V
CC
EE
TTL
N/A
n
2
Power Supply
Pass Through D[0:10]
PECL
3.3 V
5.0 V
* Pins will default LOW when left open.
N/A
†SETMIN will override SETMAX if both pins are high.
Max Delay Path
n
Min Delay Path
PIN
IN*, IN*
EN*
D[0:10]*
Q, Q
LEN*
SETMIN*†
SETMAX*
CASCADE,
CASCADE
V
V
V
V
V
FTUNE
Normal Mode
Normal Mode
Latch D[0:10]
CMOS Mode
Q Logic Low
TTL Mode**
BB
CC
EE
CF
EF
ECL Mode
Q = IN
CF
NECL
N/A
n
and V
FUNCTION
ECL Signal Input
ECL Input Enable
CMOS, ECL, or TTL Select Inputs
ECL Signal Output
ECL Latch Enable
ECL Minimum Delay Set
ECL Maximum Delay Set
ECL Cascade Signal
Output Reference Voltage
Positive Supply
Negative Supply
CMOS, ECL, or TTL Input Select
ECL Reference Mode Connection
Fine Tuning Input
PIN DESCRIPTION
EE
pin.

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