nb6lq572 ON Semiconductor, nb6lq572 Datasheet - Page 6

• Manufacturer Part Number: nb6lq572
• Description: 2.5v / 3.3v Differential 4 1 Mux W/input Equalizer To 1 2 Lvpecl Clock/data Fanout / Translator
• Manufacturer: ON Semiconductor

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
11. Measured using a V
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
17. Input voltage swing is a single−ended measurement operating in differential mode.
Table 6. AC CHARACTERISTICS
f
f
f
V
t
t
t
tskew
t
F
t
t
V
t
MAX
DATAMAX
SEL
PLH
PHL
PD Tempco
DC
JITTER
r,
OUTPP
FN
INPP
, t
Figure 3. Clock Output Voltage Amplitude (V
N
Symbol
(20% − 80%).
the delays are measured from cross−point of the inputs to the cross−point of the outputs.
inputs.
f
,
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Maximum Input Clock Frequency
Maximum Operating Data Rate
Maximum Toggle Frequency, SELx
Output Voltage Amplitude (@ V
Propagation Delay to Differential Outputs
Measured at Differential Crosspoint
Differential Propagation Delay Temperature Coefficient
Output – Output skew (within device) (Note 13)
Device – Device skew (t
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
Phase Noise, f
Integrated Phase Jitter (Figure 1) fin = 1GHz, 12 kHz − 20 MHz Offset (RMS)
Random Clock Jitter, RJ(RMS), (Note 14)
Deterministic Jitter, DJ (Note 15)
Crosstalk Induced Jitter (Adjacent Channel) (Note 16)
Input Voltage Swing (Differential Configuration) (Note 17)
Output Rise/Fall Times @ 1 GHz; (20% − 80%), Qx, Qx
INPPmin
source, 50% duty cycle clock source. All output loading with external 50 W to V
in
= 1 GHz
900
850
800
750
700
650
600
550
500
0
V
pdmax
CC
= 2.375 V to 3.6 V, GND = 0 V, T
1.0
– t
Q AMP (mV)
INPPmin
f
Characteristic
pdmin
in
, CLOCK INPUT FREQUENCY (GHz)
2.0
)
) f
OUTPP
in
http://onsemi.com
≤ 5 GHz (Note 11) (Figures 3 and 10)
3.0
) vs. Input Frequency (f
4.0
6
INx/INx to Qx/Qx @1 GHz
@ 50 MHz SELn to Qx
V
NRZ, (PRBS23)
OUT
5.0
f
w 450 mV
in
A
= 1 GHz
100 kHz
= −40°C to +85°C (Note 11)
10 MHz
20 MHz
10 kHz
1 MHz
6.0
7.0
in
) at Ambient Temperature (Typical)
8.0
Min
450
100
100
6.5
45
25
5
4
CC
− 2 V. Input edge rates 40 ps
−134
−136
−149
−150
−150
Typ
800
175
100
0.2
10
30
50
35
50
6
8
5
0
1200
Max
250
100
0.8
0.7
10
15
55
10
75
psRMS
Dfs/°C
Gbps
GHz
MHz
Unit
dBc
mV
mV
ps
ns
ps
ps
ps
%
fs