w83194br-372 Winbond Electronics Corp America, w83194br-372 Datasheet - Page 10
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w83194br-372
Manufacturer Part Number
w83194br-372
Description
Clock Generator For Sis 746/748 Chipsets
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W83194BR-372.pdf
(23 pages)
7.4 Register 3: AGP, 24_48MHz, 48MHz, REF Control (1 =Enable, 0 =Stopped)
7.5 Register 4: IOAPIC, ZCLK Control (1 = Enable, 0 = Stopped) (Default: F0h)
7.6 Register 5: 24_48MHz Control (Default: 88h)
BIT
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
(Default: FFh)
SEL24_48
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SEL<2>
SEL<1>
SEL<0>
PIN NO
PIN NO
NAME
30
31
26
27
47
46
10
4
3
2
9
-
-
PWD
PWD
PWD
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
0
0
0
AGP_1 output control
AGP_0 output control
24_48MHz output control
48MHz output control
REF2 output control
REF1 output control
REF0 output control
Reserved
IOAPIC1 output control
IOAPIC0 output control
ZCLK1 output control
ZCLK0 output control
Reserved
Asynchronous ZCLK/AGP/PCI frequency table selection, SEL<2:0>
24 / 48 MHz output selection, 1: 24 MHz (Default), 0: 48 MHz.
Reserved
Reserved
Reserved
001: 132 / 66 / 33M
011: 132 / 88 / 44M
101: 132 / 66 / 33M
111: 132 / 88 / 33M
- 7 -
DESCRIPTION
DESCRIPTION
DESCRIPTION
010:132 / 75.43 / 37.7M
100:176 / 88 / 44M
110:132 / 75.43 / 33M
000: Clock from PLL1
Publication Release Date: April 13, 2005
W83194BR-372
Revision 1.1