w83194br-730 Winbond Electronics Corp America, w83194br-730 Datasheet - Page 3

• Manufacturer Part Number: w83194br-730
• Description: 166mhz Clock For Sis Chipset
• Manufacturer: Winbond Electronics Corp America

4.2 CPU, SDRAM, PCI, AGP Clock Outputs
CPUC0$
CPUT0$
CPUCS_C1$
SDRAM [ 0:7],12
SDRAM 8/PD#
SDRAM9/
SDRAM_STOP#
SDRAM 10/
PCI_STOP#
SDRAM 11/
CPU_STOP#
PCICLK0^/&FS1
PCICLK1^/&FS2
PCICLK [2:4]^
PCICLK5/
RESET$
AGPCLK0/
SEL24#_48*
AGPCLK1/
Mode1*
SYMBOL
42,41,40,38,37
,36,34,33, 26
10,11,12
47,46
PIN
45
31
30
28
27
13
16
17
8
9
OUT
OUT
OUT
OUT
OUT
OUT
OD
OD
I/O
I/O
I/O
I/O
I/O
I/O
- 3 -
Open drain output clock for host frequencies CPU.
Powered by VddLCPU. Stopped if CPU_STOP# is
low.
Open drain clock for chipset. Stopped if CPU_STOP#
is low and Register1 bit7=0. The same phase as
CPUC0$.
SDRAM clock outputs. The same phase as CPUC0$
Pin21 &Mode=0, SDRAM clock outputs.
Pin21 &Mode=1, PD# input
Pin21 &Mode=0, SDRAM clock outputs.
Pin21 &Mode=1, SDRAM_STOP# input
Pin21 &Mode=0, SDRAM clock outputs.
Pin21 &Mode=1, PCI_STOP# input
Pin21 &Mode=0, SDRAM clock outputs.
Pin21 &Mode=1, CPU_STOP# input
Low skew (< 250ps) PCI clock outputs.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Low skew (< 250ps) PCI clock outputs.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Low skew (< 250ps) PCI clock outputs.
Latched Input.
PCI clock during normal operation. (pin 17 MODE1=1)
If pin17 MODE1=0, RESET# (open drain, 4ms low
active pulse when Watch Dog time out)
Low skew (< 250ps) AGP clock output.
Latched Input. SEL24#_48*=1, Pin 21 is 24MHz;
SEL24_48*=0, Pin21 is 48MHz
AGP clock outputs
Latched Input. Mode1*=1, Pin 13 is PCICLK;
Mode1*=0, Pin13 is RESET#
Publication Release Date:Oct. 2000
FUNCTION
W83194BR-730
PRELIMINARY
Revision 0.60