w83194br-603 Winbond Electronics Corp America, w83194br-603 Datasheet - Page 13

• Manufacturer Part Number: w83194br-603
• Description: Winbond Clock Generator For Intel P4 Springdale Series Chipset
• Manufacturer: Winbond Electronics Corp America

7.6
7.7
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Register 5: Watchdog Control Register (Default: 02h)
Register 6: Winbond Chip ID Register (Default: 60h) (Read Only)
SEL24_48
EN_WD
WD_TIMEOUT
SAF_FREQ [4]
SAF_FREQ [3]
SAF_FREQ [2]
SAF_FREQ [1]
SAF_FREQ [0]
MAS_VER_ID [1]
MAS_VER_ID [0]
SUB_VER_ID [1]
SUB_VER_ID [0]
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
MAS_ID [1]
MAS_ID [0]
SUB_ID [1]
SUB_ID [0]
NAME
NAME
PWD
X
0
0
0
0
0
1
0
PWD
24 / 48 MHz output selection, 1: 24 MHz.0: 48 MHz. (Default)
Default value follow hardware trapping data on SEL24_48# pin.
Program this bit =>
1: Enable Watchdog Timer feature.
0: Disable Watchdog Timer feature.
Read-back this bit =>
During timer count down the bit read back to 1.
If count to zero, this bit read back to 0.
Read Back only. Timeout Flag. This bit is Read Only.
1: Watchdog has ever started and counts to zero.
0: Watchdog is restarted and counting.
These bits will be reloaded in Reg-0 to select frequency table. As the
watchdog is timeout and EN_SAFE_FREQ=1.
0
1
1
0
0
0
0
0
MASK definition for master body
*A****: 01, *B****: 10, *C****: 11, *D****:00
MASK definition for code body
*A****001: 01,
MASK version definition for master body
*A****001AA: 00, *A****001AB: 01,
*A****001AC: 10, *A****001AD: 11.
MASK version definition for code body
*A****001A: 00, *A****001B: 01 *A****001C: 10, *A****001D: 11
W83194BR-603/W83194BG-603
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*A****002:
DESCRIPTION
DESCRIPTION
10, *A****003: 11,
Publication Release Date: March, 2006
*A****004:00
Revision 0.7