w83176g-733 Winbond Electronics Corp America, w83176g-733 Datasheet
w83176g-733
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w83176g-733 Summary of contents
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... W83176R-733 W83176G-733 Winbond Dual Bank DDR BUFFER For VIA CHIPSET Date: Mar/22/2006 Revision: 1.0 ...
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... DUAL BANK DDR BUFFER FOR VIA CHIPSET W83176R-733/W83176G-733 Data Sheet Revision History PAGES DATES 1 2 n.a. 09/09/03 3,4,5,8 12/18/ 03/22/2006 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners ...
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... Register 23: Slew Rate Control (Default: AAh) .......................................................................9 8. ACCESS INTERFACE .............................................................................................................. 10 8.1 Block Write Protocol ...............................................................................................................10 8.2 Block Read Protocol...............................................................................................................10 8.3 Byte Write Protocol.................................................................................................................10 8.4 Byte Read Protocol ................................................................................................................10 9. SPECIFICATIONS .................................................................................................................... 11 9.1 ABSOLUTE MAXIMUM RATINGS .......................................................................................11 9.2 AC CHARACTERISTICS.......................................................................................................11 9.3 DC CHARACTERISTICS ......................................................................................................11 10. ORDERING INFORMATION..................................................................................................... 12 11. HOW TO READ THE TOP MARKING...................................................................................... 12 12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 13 W83176R-733/W83176G-733 - 2 - ...
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... F_I Internal pull-up resistor 120K to VDD W83176R-733/W83176G-733 ...
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... DUAL BANK DDR BUFFER FOR VIA CHIPSET 4. BLOCK DIAGRAM BUF_INA BUF_INB SCLK* Control SDATA* Logic OE_ODD* OE_EVEN* W83176R-733/W83176G-733 - 4 - FB_OUTA DDRAT[5:0] DDRAC[5:0] FB_OUTB DDRBT[5:0] DDRBC[5:0] ...
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... Control Signal Pins PIN PIN NAME 26 SDATA * 25 SCLK * 45 OE_EVEN* 46 OE_ODD* W83176R-733/W83176G-733 DESCRIPTION Input Output Bi-directional Pin, Open Drain Internal 120kΩ pull-up TYPE IN Bank A DDR Buffer True reference clock input. OUT Bank A DDR Buffer clocks of differential pair outputs. Bank A DDR Buffer True Feedback output, dedicated for OUT external feedback ...
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... W83176R-733/W83176G-733 PIN NAME GND Ground VDD2.5 Power Supply 2.5V DESCRIPTION Reserved FB_OUTA output control DDRA_T5/C5 output control DDRA_T4/C4 output control DDRA_T3/C3 output control DDRA_T2/C2 output control DDRA_T1/C1 output control DDRA_T0/C0 output control Description Reserved FB_OUTB output control ...
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... Register 19: Skew Control (Default: 80h) BIT NAME 7 Reserved 6 DDRB_CSKEW<2> 5 DDRB_CSKEW<1> 4 DDRB_CSKEW<0> 3 FAOUT_SKEW<1> 2 FAOUT_SKEW<0> 1 FBOUT_SKEW<1> 0 FBOUT_SKEW<0> W83176R-733/W83176G-733 PWD 1 Reserved 0 DDRA True clock outputs with FB_OUTA True clock SKEW control bits Reserved 0 DDRA Complementary clock outputs with FB_OUTA True clock SKEW control bits 0 0 PWD 1 Reserved ...
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... BIT NAME 7 DDRAT/C2_SR<1> 6 DDRAT/C2_SR<0> 5 DDRAT/C3_SR<1> 4 DDRAT/C3_SR<0> 3 DDRAT/C4_SR<1> 2 DDRAT/C4_SR<0> 1 DDRAT/C5_SR<1> 0 DDRAT/C5_SR<0> W83176R-733/W83176G-733 Normal (default) Strong Weak PWD 1 Reserved 0 DDRB True clock outputs with FB_OUTB True clock SKEW control bits DDRAT/C0 slew rate control bits 0 1 DDRAT/C1 slew rate control bits 0 PWD ...
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... BIT NAME 7 DDRBT/C4_SR<1> 6 DDRBT/C4_SR<0> 5 DDRBT/C5_SR<1> 4 DDRBT/C5_SR<0> 3 FBOUT_SR<1> 2 FBOUT_SR<0> 1 FAOUT_SR<1> 0 FAOUT_SR<0> W83176R-733/W83176G-733 PWD 1 DDRBT/C0 slew rate control bits 0 1 DDRBT/C1 slew rate control bits 0 1 DDRBT/C2 slew rate control bits 0 1 DDRBT/C3 slew rate control bits 0 PWD 1 DDRBT/C4 slew rate control bits 0 ...
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... W83176R-733 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I address is defined at 0xD4. The I 8.1 Block Write Protocol 8.2 Block Read Protocol ## In block mode, the command code must filled ‘00h’ 8.3 Byte Write Protocol 8.4 Byte Read Protocol W83176R-733/W83176G-733 2 C read address is defined at 0xD5 write ...
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... A PARAMETER SDATA, SCLK Input Low Voltage SDATA, SCLK Input High Voltage BUF_IN Input Voltage Low BUF_IN Input Voltage High Input Pin Capacitance Output Pin Capacitance Input Pin Inductance W83176R-733/W83176G-733 ° ° +70 C, Test load = 10 pF SYMBOL MIN TYP F 100 IN Dtin ...
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... G W83176G-733 28051234 342 AASA G 1st line: Winbond logo and the type number: Normal:W83176R-733, Lead free part: W83176G-733 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 342: packages made in '2003, week 42 G: assembly house ID ...
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... SEATING PLANE e PARTING LINE b SIDE VIEW c θ Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. W83176R-733/W83176G-733 SYMBOL .045 .055 A A1 END VIEW HE A2 ...
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... Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83176R-733/W83176G-733 Important Notice - 14 - ...