cy7b9945v Cypress Semiconductor Corporation., cy7b9945v Datasheet - Page 7

• Manufacturer Part Number: cy7b9945v
• Description: High-speed Multi-phase Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07336 Rev. *E
Capacitance
Switching Characteristics
C
f
f
t
t
t
t
t
t
t
t
TTB
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
10. Each package must be properly decoupled.
11. AC parameters are measured at 1.5V, unless otherwise indicated.
12. Test Load C
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when
14. Tested initially and after any design or process changes that may affect these parameters.
15. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply
16. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
17. Rise and fall times are measured between 2.0V and 0.8V.
18. f
19. t
Parameter
in
out
SKEWPR
SKEWBNK
SKEW0
SKEW1
SKEW2
CCJ1-3
CCJ4-12
PD
PDDELTA
REFpwh
REFpwl
r
LOCK
RELOCK1
RELOCK2
ODCV
PWH
PWL
PDEV
OAZ
OZA
7.
8.
9.
/t
IN
f
Parameter
This is for non-three-level inputs.
Assumes 25 pF Max. Load Capacitance up to 185 MHz. At 200 MHz the max. load is 10 pF.
Both outputs of pair must be terminated, even if only one is being used.
all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output
skew, cycle-cycle jitter, and dynamic phase error. TTB will be equal to or smaller than the maximum specified value at a given output frequency.
NOM
PWH
must be within the frequency range defined by the same FS state.
is measured at 2.0V. t
Clock Input Frequency
Clock Output Frequency
Matched-Pair Skew
Intrabank Skew
Output-Output Skew (same frequency and phase, rise to rise, fall to fall)
Output-Output Skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall)
Output-Output Skew (all output configurations outside of t
t
Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3)
Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5,
6, 8, 10, 12)
Propagation Delay, REF to FB Rise
Total Timing Budget window (same frequency and phase)
Propagation Delay difference between two devices
REF input (Pulse Width HIGH)
REF input (Pulse Width LOW)
Output Rise/Fall Time
PLL Lock TIme From Power-Up
PLL Relock Time (from same frequency, different phase) with Stable
Power Supply
PLL Re-Lock Time (from different frequency, different phase) with Stable
Power Supply
Output duty cycle deviation from 50%
Output HIGH time deviation from 50%
Output LOW time deviation from 50%
Period deviation when changing from reference to reference
DIS[1:2] HIGH to output high-impedance from ACTIVE
DIS[1:2] LOW to output ACTIVE from output is high-impedance
L
SKEW1
= 25 pF, terminated to V
Input Capacitance
)
[12, 13]
Description
PWL
[18]
[12, 13]
is measured at 0.8V.
[12, 13]
CC
Over the Operating Range
[17]
/2 with 50Ω up to185 MHz and 10-pF load to 200 MHz.
,1Q[0:1],1Q[2:3],2Q[0:1],2Q[2:3],2Q[4:5]
Description
[5]
[5]
T
A
= 25
[19]
[11]
[19]
°
C, f = 1 MHz, V
[12, 13]
Test Conditions
[7, 8, 9, 10, 11]
[16]
[12, 21]
CC
SKEW0
[14, 15]
= 3.3V
[20]
[21, 22]
and
[12, 13]
CY7B9945V-2 CY7B9945V-5
–250
Min.
0.15
–1.0
2.0
2.0
1.0
0.5
24
24
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.025
Max.
1000
200
200
200
250
250
250
500
150
100
250
500
200
500
2.0
1.0
1.5
2.0
10
10
14
–
–
Min.
–
–500
Min.
0.15
–1.0
2.0
2.0
1.0
0.5
24
24
RoboClock
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY7B9945V
Max.
0.025
Max.
1000
5
200
200
200
250
550
650
800
150
100
500
700
200
500
2.0
1.0
1.5
2.0
10
10
14
–
–
Page 7 of 10
Peak-
Peak-
Peak
Peak
MHz
MHz
Unit
Unit
ms
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
UI
pF

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