lmk04000b National Semiconductor Corporation, lmk04000b Datasheet - Page 34

• Manufacturer Part Number: lmk04000b
• Description: Low-noise Clock Jitter Cleaner With Cascaded Plls
• Manufacturer: National Semiconductor Corporation

www.national.com
16.3.5 CLKoutX/CLKoutX* LVPECL Mode Control
Clock outputs designated as LVPECL can be configured in
one of two possible output levels. The default mode is the
common LVPECL swing of 800 mVp-p single-ended (1.6 Vp-
p differential). A second mode, 2VPECL, can be enabled in
which the swing is increased to 1000 mVp-p single-ended (2
Vp-p differential).
16.3.6 CLKoutX_MUX: Clock Output Mux
The output of each CLKoutX channel pair is controlled by its'
channel multiplexer (mux). The mux can select between sev-
eral signals: bypassed, divided only, divided and delayed, or
delayed only.
16.4 REGISTERS 5, 6
These registers are reserved. These register values should
not be modified from the values shown in the register map.
16.5 REGISTER 7
16.5.1 RESET bit
This bit is only in register R7. The use of this bit is optional
and it should be set to '0' if not used. Setting this bit to a '1'
forces all registers to their power on reset condition and there-
fore automatically clears this bit.
16.6 REGISTERS 8, 9
These registers are reserved. These register values should
not be modified from the values shown in the register map.
16.7 REGISTER 10
16.7.1 RC_DLD1_Start: PLL1 Digital Lock Detect Run
Control bit
This bit is used to control the state machine for the PLL2 VCO
tuning algorithm. The following table describes the function of
this bit.
TABLE 8. CLKoutX_MUX: Clock Channel Multiplexer
CLKoutX_PECL_LVL
CLKout_MUX [1:0]
b1
0
0
1
1
TABLE 7. LVPECL Output Format Control
0
1
b0
0
1
0
1
Control Bits
2VPECL (1000 mVpp)
LVPECL (800 mVpp)
Divided and Delayed
Output Format
Clock Mode
Bypassed
Delayed
Divided
34
If the user is unsure of the state of the reference clock input
at startup of the LMK040xx device, setting RC_DLD1_Start =
0 will allow PLL2 to tune and lock the internal VCO to the
oscillator attached to the OSCin port. This ensures that the
active clock outputs will start up at frequencies close to their
desired values. The error in clock output frequency will de-
pend on the open loop accuracy of the oscillator driving the
OSCin port. The frequency of an active clock output is nor-
mally given by:
If the open loop frequency accuracy of the external oscillator
(either a VCXO or crystal based oscillator) is "X" ppm, then
the error in the output clock frequency (F
Setting this bit to 0 does not prevent PLL1 from locking the
external oscillator to the reference clock input after the latter
input becomes valid.
16.8 REGISTER 11
16.8.1 CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer
Mode Control
The user may choose between one of two input buffer modes
for the PLL1 reference clock inputs: either bipolar junction
differential or MOS. Both CLKinX and CLKinX* input pins
must be AC coupled when driven differentially. In single end-
ed mode, the CLKinX* pin must be coupled to ground through
a capacitor. The active CLKinX buffer mode is selected by the
CLKinX_TYPE bits programmed via the uWire interface.
RC_DLD
TABLE 10. PLL1 CLKinX_BUFTYPE Mode Control Bits
1_Start
1
0
b1
0
0
1
1
TABLE 9. RC_DLD1_Start bit states
immediately after any PLL2_N counter update,
delayed until PLL1 Digital Lock Detect is valid.
despite the state of PLL1 Digital Lock Detect.
The PLL2 VCO tuning algorithm trigger is
The PLL2 VCO tuning algorithm runs
b0
0
1
0
1
BJT Differential BJT Differential
BJT Differential
CLKin1_TYPE
Description
MOS
MOS
CLK
BJT Differential
CLKin0_TYPE
error) will be:
30027160
30027161
MOS
MOS