max9205eait Maxim Integrated Products, Inc., max9205eait Datasheet - Page 6

• Manufacturer Part Number: max9205eait
• Description: 10-bit, Bus Lvds Serializers
• Manufacturer: Maxim Integrated Products, Inc.

When V
impedance and internal circuitry is disabled by on-chip
power-on-reset circuitry. When V
PLL starts to lock to a local reference clock (16MHz to
40MHz for MAX9205 and 40MHz to 66MHz for
MAX9207). The reference clock, TCLK, is provided by
the system. A serializer locks within 2049 cycles of
TCLK. Once locked, a serializer is ready to send data
or SYNC patterns depending on the levels of SYNC 1
and SYNC 2.
To rapidly synchronize with a deserializer, SYNC pat-
terns can be sent. A SYNC pattern is six consecutive
ones followed by six consecutive zeros repeating every
TCLK period. When one or both SYNC inputs are
asserted high for at least six cycles of TCLK, the serial-
izer will initiate the transmission of 1024 SYNC patterns.
The serializer will continue to send SYNC patterns if
either of the SYNC input pins remains high. Toggling
one SYNC input with the other SYNC input low before
1024 SYNC patterns are output does not interrupt the
output of the 1024 SYNC patterns.
After initialization, both SYNC input pins must be set
low by users or through a control signal from the dese-
rializer before data transmission begins. Provided that
SYNC inputs are low, input data at IN0–9 are clocked
into the serializer by the TCLK input. Setting TCLK_R/F
high selects the rising edge of TCLK for data strobe
and low selects the falling edge. If either of the SYNC
inputs goes high for six TCLK cycles at any time during
10-Bit Bus LVDS Serializers
Table 1. Input /Output Function Table
X = Don’t care
6
_______________________________________________________________________________________
EN
H
H
X
L
CC
is applied, the outputs are held in high
PWRDN
H
H
L
X
Data Transmission Mode
INPUTS
Synchronization Mode
and SYNC 2 are held high for
When either or both SYNC 1
SYNC 1
Initialization Mode
at least six TCLK cycles
CC
L
X
X
reaches 2.35V, the
SYNC 2
L
X
X
Synchronization Mode. SYNC patterns of six 1s and six 0s are
transmitted every TCLK cycle for at least 1024 TCLK cycles.
Data at IN0–9 are ignored.
Data Transmission Mode. IN0–9 and 2 frame bits are
transmitted every TCLK cycle.
Output in high-impedance.
data transmission, the data at IN0–9 are ignored and
SYNC patterns are sent for at least 1024 TCLK cycles.
A start bit high and a stop bit low frame the 10-bit data
and function as the embedded clock edge in the serial
data stream. The serial rate is the TCLK frequency
times the data and appended bits. For example, if
TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) =
480Mbps. Since only 10 bits are from input data, the
payload rate is 40 x 10 = 400Mbps.
Power-down mode is entered when the PWRDN pin is
driven low. In power-down mode, the PLL of the serial-
izer is stopped and the outputs (OUT+ and OUT-) are
in high impedance, disabling drive current and also
reducing supply current. When PWRDN is driven high,
the serializer must reinitialize and resynchronize before
data can be transferred.
The serializer output pins (OUT+ and OUT-) are held in
high impedance when V
PLL is locking to the local reference clock. Setting EN
or PWRDN low puts the device in high impedance.
After initialization, EN functions asynchronously. For
example, the serializer output can be put into high
impedance while SYNC patterns are being sent without
affecting the internal timing of the SYNC pattern gener-
ation. However, if the serializer goes into high imped-
ance, a deserializer loses PLL lock and needs to
resynchronize before data transfer can resume.
OUT+, OUT-
OUTPUTS
CC
High-Impedance State
is first applied and while the
Power-Down