max9325eqit Maxim Integrated Products, Inc., max9325eqit Datasheet - Page 9

• Manufacturer Part Number: max9325eqit
• Description: Max9325 2 8 Differential Lvpecl/lvecl/hstl Clock And Data Driver
• Manufacturer: Maxim Integrated Products, Inc.

Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram
The MAX9325 low-skew, 2:8 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make the
device ideal for clock and data distribution across a
backplane or board. The device selects one of the two
differential HSTL or LVECL/LVPECL inputs, and repeats
them at eight differential outputs. Outputs are compati-
ble with LVECL and LVPECL, and can directly drive 50Ω
terminated transmission lines.
A 2:1 mux selects between the two differential inputs,
CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched
by the single-ended CLK_SEL input. A logic low selects
the CLK0, CLK0 input. A logic high selects the CLK1,
CLK1 input. The logic threshold for CLK_SEL is set by
an internal V
reproduced at eight differential outputs at speeds up to
700MHz.
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output volt-
age (V
or a differential input of at least 95mV switches the out-
puts to the V
Electrical Characteristics. The maximum magnitude of
the differential input from CLK_ to CLK_ is ±3.0V or
2:8 Differential LVPECL/LVECL/HSTL Clock and
BB
CLK_ WHEN CLK_ = V
CLK_ WHEN CLK_ = V
). A single-ended input of at least V
Q_
Q_
OR
BB
OH
voltage reference. The selected input is
and V
_______________________________________________________________________________________
BB
BB
Detailed Description
OL
levels specified in the DC
V
V
BB
BB
t
PLH
BB
±95mV
±(V
to the difference between a single-ended input and any
reference voltage input.
The single-ended CLK_SEL input has a 75kΩ pulldown
to V
CLK_SEL is left open or at V
have 105kΩ pulldowns to V
fail-safe circuit ensure differential low default outputs
when the inputs are left open or at V
Specifications for the high and low voltages of a differ-
ential input (V
voltage (V
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.375V to +3.8V supply
range, allowing high-performance clock or data distrib-
ution in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.375V to -3.8V supply.
CLK_SEL is a single-ended input with the input threshold
internally set to V
by a single-ended LVPECL/LVECL signal. The CLK_,
CLK_ are differential inputs but can be configured to
accept single-ended inputs when operating at supply
voltages greater than 2.58V. The recommended supply
voltage for single-ended operation is 3.0V to 3.8V. A dif-
V
CC
OH
EE
- V
OL
that selects the default input, CLK0, CLK0, when
- V
EE
IHD
), whichever is less. This limit also applies
- V
IHD
ILD
BB
and V
, and can be driven to V
) apply simultaneously.
V
V
t
BB
BB
PHL
ILD
Single-Ended Operation
EE
EE
Data Driver
) and the differential input
. Internal pulldowns and a
. All the differential inputs
EE
.
CC
V
V
V
V
V
V
IH
IL
IH
IL
OH
OL
or V
EE
or
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