74hct40105 NXP Semiconductors, 74hct40105 Datasheet - Page 14

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74hct40105

Manufacturer Part Number
74hct40105
Description
4-bit X 16-word Fifo Register
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
Shift-out operation; high-speed burst mode
1998 Jan 23
4-bit x 16-word FIFO register
In the high-speed mode, the burst-out rate is determined by the
minimum shift-out HIGH and shift-out LOW specifications. The
DOR flag is a don’t care condition and a SO pulse can be applied
without regard to the flag.
(1) HC : V
Fig.12 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out
The shaded areas indicate when the input is permitted
to change for predictable output performance.
(1) HC : V
(1) HC : V
HCT : V
HCT : V
HCT : V
burst mode.
Fig.14 Waveforms showing SO input to Q
M
M
M
M
M
M
= 50%; V
= 1.3 V; V
= 50%; V
= 1.3 V; V
= 50%; V
= 1.3 V; V
I
I
I
I
I
I
= GND to V
= GND to V
= GND to V
Fig.13 Waveforms showing hold and set up times for D
= GND to 3 V.
= GND to 3 V.
= GND to 3 V.
CC
CC
CC
.
.
.
n
output propagation delays and output transition time.
14
n
input to SI input.
74HC/HCT40105
Product specification

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