74hct7030 NXP Semiconductors, 74hct7030 Datasheet - Page 13

• Manufacturer Part Number: 74hct7030
• Description: 9-bit X 64-word Fifo Register; 3-state
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Master reset applied with FIFO full
Shifting out sequence; FIFO full to FIFO empty
December 1990
9-bit x 64-word FIFO register; 3-state
(1) HC : V
Fig.8
(1) HC : V
Fig.9
HCT: V
HCT: V
Waveforms showing the MR input to DIR, DOR output
propagation delays and the MR pulse width.
Waveforms showing the SO input to DIR output propagation
delay. The SO pulse width and SO maximum pulse frequency.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
CC
CC
.
.
13
Notes to Fig.8
1. DIR LOW, output ready HIGH;
2. MR pulse LOW; clears FIFO.
3. DIR goes HIGH; flag indicates
4. DOR drops LOW; flag indicates
Notes to Fig.9
1. DOR HIGH; no data transfer in
2. SO set HIGH; results in DOR
3. DOR drops LOW; output stage
4. SO is set LOW; data in the input
5. DOR goes HIGH; transfer
6. Repeat process to unload the 3rd
7. DOR remains LOW; FIFO is
assume FIFO is full.
input prepared for valid data.
FIFO empty.
progress, valid data is present at
output stage.
going LOW.
“busy”.
stage is unloaded, and new data
replaces it as empty location
“bubbles-up” to input stage.
process completed, valid data
present at output after the
specified propagation delay.
through to the 64th word from
FIFO.
empty.
74HC/HCT7030
Product specification