74hct7030 NXP Semiconductors, 74hct7030 Datasheet - Page 19

• Manufacturer Part Number: 74hct7030
• Description: 9-bit X 64-word Fifo Register; 3-state
• Manufacturer: NXP Semiconductors

Philips Semiconductors
December 1990
9-bit x 64-word FIFO register; 3-state
(1) HC : V
Fig.20 FIFO to FIFO communication; input timing under empty condition.
HCT: V
M
M
= 50%; V
= 1.3 V; V
I
I
= GND to V
= GND to 3 V.
CC
.
19
Notes to Fig.20
1. FIFO
2. Load one word into FIFO
3. Data out
4. DOR
5. DIR
6. DIR
7. DOR
SO
data.
pulse applied, results in DIR
pulse.
valid data arrives at FIFO
stage after a specified delay of
the DOR flag, meeting data input
set-up requirements of FIFO
(ripple through delay after
SI
FIFO
output ready pulse, data is shifted
into FIFO
indicates input stage of FIFO
busy, shift-out of FIFO
complete.
automatically; the input stage of
FIFO
data, SO is held HIGH in
anticipation of additional data.
delay after SI
present one propagation delay
later at the FIFO
A
A
LOW) data is unloaded from
B
B
held HIGH in anticipation of
A
B
A
A
B
and SO
and SO
74HC/HCT7030
and SI
goes HIGH; (ripple through
and FIFO
as a result of the data
is again able to receive
A
B
/data in
.
Product specification
B
B
A
A
LOW) valid data is
pulse HIGH;
go LOW; flag
go HIGH
B
B
initially empty,
output stage.
B
transition;
A
is
A
A
; SI
output
B
B
.
is