adf4212l Analog Devices, Inc., adf4212l Datasheet
adf4212l
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adf4212l Summary of contents
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... Analog Devices. Trademarks and registered trademarks are the property of their respective companies. GENERAL DESCRIPTION The ADF4212L is a dual frequency synthesizer that can be used to implement local oscillators (LO) in the up-conversion and down-conversion sections of wireless receivers and transmitters. ...
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... ADF4212L–SPECIFICATIONS AGND = DGND = unless otherwise noted; dBm referred MIN MAX Parameter RF/IF CHARACTERISTICS RF Input Frequency ( Input Sensitivity IF Input Frequency ( Input Sensitivity MAXIMUM ALLOWABLE 3 Prescaler Output Frequency REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity ...
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... Offset and 1 MHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency See Note 7 See Note 7 See Note 7 @ 200 kHz/400 kHz and 200 kHz PFD Frequency to 5.5 V; AGND = DGND = AGND DB0 (LSB) (CONTROL BIT C1 ADF4212L = DGND = ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4212L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... for both the RF and IF charge pumps. CP MAX 2 should have a value of between 2.6 V and 3 –5– ADF4212L LFCSP DGND DGND ADF4212L AGND TOP VIEW IF (NOT TO SCALE) R AGND 4 12 SET RF 11 ...
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... ADF4212L–Typical Performance Characteristics –5 –10 –15 –20 –25 –30 0 500 1000 1500 FREQUENCY – MHz TPC 1. Input Sensitivity (RF Input –5 –10 –15 –20 –25 –30 –35 0 500 FREQUENCY – MHz TPC 2. Input Sensitivity (IF Input) ...
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... TPC 11. RF Charge Pump Output Characteristics –2 –4 –6 1000 10000 TPC 12. IF Charge Pump Output Characteristics –7– ADF4212L 100 1000 PHASE DETECTOR FREQUENCY – kHz – – ...
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... ADF4212L 0 –20 –40 –60 –80 –100 TUNING VOLTAGE – V TPC 13. RF Reference Spurs (200 kHz) vs. V (1750 MHz, 200 kHz, 20 kHz) 0 –20 –40 –60 –80 –100 –120 TUNING VOLTAGE – V TPC 14. IF Reference Spurs (200 kHz) vs. V (1750 MHz, 200 kHz, 20 kHz) 0 – ...
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... RF/IF Input Stage The RF/IF Input Stage is shown in Figure followed by a two-stage limiting amplifier to generate the CML (Current Mode Logic) clock levels needed for the prescaler COUNTER RF BUFFER –9– ADF4212L FREQ s11.REAL s11.IMAG (MHz) s11.REAL s11.IMAG 1550 0.561872 0.97692 – ...
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... MUXOUT and Lock Detect The output multiplexer on the ADF4212L allows the user to REFIN access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11, and P12. See Table III and Table V. Figure 6 shows the MUXOUT section in block diagram form. ...
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... RF/IF Input Shift Register The ADF4212L digital section includes a 24-bit input shift register, a 14-bit IF R counter, and an 18-bit IF N counter (comprising a 6-bit IF A counter and a 12-bit IF B counter). Also present is a 14-bit RF R counter and an 18-bit RF N counter (comprising a 6-bit RF A counter and a 12-bit RF B counter) ...
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... ADF4212L IF R COUNTER LATCH IF CP CURRENT SETTING DB23 DB22 DB21 DB20 DB19 DB18 DB17 IFCP2 IFCP1 IFCP0 P12 P11 P4 FROM RF R LATCH ...
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... ADF4212L 6-BIT A COUNTER DB8 DB7 DB6 DB5 DB4 DB3 DB2 ( .......... COUNTER DIVIDE RATIO 0 0 .......... .......... ...
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... ADF4212L RF R COUNTER LATCH RF CP CURRENT SETTING DB23 DB22 DB21 DB20 DB19 DB18 DB17 RFCP2 RFCP1 RFCP0 P12 P11 P10 P10 0 1 P12 P11 P4 FROM IF R LATCH ...
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... ADF4212L 6-BIT A COUNTER DB8 DB7 DB6 DB5 DB4 DB3 DB2 ( .......... COUNTER DIVIDE RATIO 0 0 .......... .......... ...
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... Table III and Table V show the power-down bits in the ADF4212L. IF Fastlock The IF CP Gain Bit (P8) of the IF N Register in the ADF4212L is the Fastlock Enable Bit. Only when this is “1” Fastlock enabled. When Fastlock is enabled, the IF CP current is set to maximum value. Also, an extra loop filter damping resistor to ground is switched in using the FLO pin, thus compensating for the change in loop characteristics while in Fastlock ...
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... ADF4210 family. RF Fastlock The RF CP Gain Bit (P17) of the RF N Register in the ADF4212L is the Fastlock Enable Bit. Only when this is “1” Fastlock enabled. When Fastlock is enabled, the RF CP current is set to maximum value. Also, an extra loop filter damping resistor to ground is switched in using the FLO pin, thus compensating for the change in loop characteristics while in Fastlock ...
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... For example, cable television tuners have a total range of about 400 MHz. Figure 8 shows an application where the ADF4212L is used to control and program the Micronetics M3500-1324. The loop filter was designed for an RF output of 2100 MHz, a loop bandwidth of 40 kHz, a PFD frequency of 1 MHz ...
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... The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4212L needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer ...
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... ADF4212L 20-Lead Thin Shrink Small Outline Package [TSSOP] PIN 1 0.15 0.05 COPLANARITY 0.10 PIN 1 INDICATOR 1.00 0.90 0.80 SEATING PLANE Revision History Location 3/03—Data Sheet changed from REV REV. A. Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to Table Changes to Table Changes to Figure OUTLINE DIMENSIONS (RU-20) Dimensions shown in millimeters 6 ...