hsp48410 Intersil Corporation, hsp48410 Datasheet - Page 6

• Manufacturer Part Number: hsp48410
• Description: Histogrammer/accumulating Buffer
• Manufacturer: Intersil Corporation

Functional Block Diagram
Histogram Mode
This is the fundamental operation for which this chip was
intended. When this mode is selected, the chip configures
itself as shown in the Block Diagram of Figure 2. The pixel
data is sampled on the rising edge of clock and used as the
read address to the RAM array. The data contained in that
address (or bin) is then incremented by 1 and written back
into the RAM at the same address.
PIN 0-9
START
FIGURE 2. HISTOGRAM MODE BLOCK DIAGRAM
CONTROL
DIN 0-23
GENERATOR
IOADD 0-9
IN
ADDRESS
ADDRESS
ALL REGISTERS ARE CLOCKED BY CLK
FCT 0-2
PIN 0-9
START
RAM
UWS
CLK
WR
OUT
RD
FC
LD
WR
“0”
“1”
6
MUX
CONTROL
FUNCTION
DECODE
S
IN
GENERATOR
COUNTER
ADDRESS
ADDRESS
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
24X1024
RAM
TO ADDRESS GENERATOR
TO OUTPUT STAGE
TO RAM
DIO
RD
OUT
I/F
MUX
CONTROL
SIGNALS
0-23
DIO
HSP48410
CONTROL
ADDER
INPUT
(RD LOW)
DIO 0-23
At the same time, the new value is also displayed on the DIO
bus. This procedure continues until the circuit is interrupted
by START returning high. When START is high, the RAM
write is disabled, the read address is taken from the Pixel
Input bus, and the chip acts as if it is in LUT(read) mode.
Figure 3 shows histogram mode timing. START is used to
disregard the data on PIN0-9 at DATA2. START is sampled
on the rising edge of clock, but is delayed internally by 3
cycles to match the latency of the Address Generator. Data
is clocked onto the DIO bus on the rising edge of CLK. RD
acts as output enable.
PIN 0-9
START
CLK
FIGURE 3. HISTOGRAM MODE TIMING
DATA 0 DATA 1 DATA 2 DATA 3 DATA 4
MUX
ORIGINAL BIN CONTENTS
DIO
ARE NOT UPDATED
I/F
OUT 0 OUT 1 OUT 2
DIO 0-23
DATA 5