rtc-4553ac Epson Electronics America, Inc., rtc-4553ac Datasheet - Page 14

• Manufacturer Part Number: rtc-4553ac
• Description: Real Time Clock Module
• Manufacturer: Epson Electronics America, Inc.

RTC – 4553AC
(2) Control register 2
(3) Control register 3
(a) BUSY bit (D3)
(b) PONC bit (D2)
(c) D1 bit (bit marked "—")
(d) D0 bit (bit marked "
(a) SYSR bit (D3)
(b) TEST bit (D2)
(c) MS1, MS0 bit (D1, D0)
Control register 2 provides flags for carry detect and power-on-clear detect.
Control registers 3 serves for reading and writing data for address mode switching and making system reset
settings.
The control register 3 applies to modes 0 - 2.
The SYSR bit serves for clearing all counter registers (see section on initialization on next page).
This bit is reset by making CS0 High and SCK Low.
The BUSY bit serves for time/calendar counter digit carry detection.
If the BUSY bit is "L", carry does not occur for at least 3.9 ms. (Also when read/write is carried out at point
"a" in the chart below, carry does not occur for 3.9 ms.)
Take the processing time into consideration and design the read/write operation to complete within 3.8 ms.
Clock read/write during carry
The PONC bit is the power-on-clear detection bit (see next page). It is set to "1" when power-on-clear is
detected. The PONC bit is reset (1
When this bit is read, data are undefined.
When writing this bit, always set it to "0".
The TEST bit serves to switch the IC to the test mode.
Note Be sure to permanently set this bit to "0". Otherwise correct operation is not assured.
The MS1 and MS0 bits serve for address switching.
A3
A3
· Read It may not be possible to read correct data.
· Write Because the clock has priority, the write operation does not increment the counter.
1
MS1
1
BUSY bit
0
0
1
1
BUSY timing
0
1
A2
A2
(During carry, the result is the same as for a read operation.)
1
1
MS0
0
1
0
1
Carry pulse in IC
BUSY bit
Normal mode
A1
A1
1
1
")
Mode
Carry
Mode name
MODE 0
MODE 0
MODE 1
MODE 2
A0
A0
1
0
CNT 3 SYSR
Name
CNT 2 BUSY PONC
Name
Time/calendar counter read/write prohibited
Time/calendar counter read/write possible
0) by setting the SYSR bit to "1".
Read/write possible
User RAM area (RA
D3
User RAM area (RA
Time/calendar counters and control registers 1 - 3
Time/calendar counters and control registers 1 - 3
D3
Page - 11
1 s
TEST
Meaning
D2
“a”
D2
3.9 ms
MS
D1
D1
—
60
1
0
Content
- RA
- RA
MS
D0
D0
59
119
Approx 0.5 s
) and control register 3
0
) and control register 3
Read/write prohibited (clock/calendar)
Register contents
Control register 3
Register contents
Control register 2
MQ - 342 - 01