max5187beeg Maxim Integrated Products, Inc., max5187beeg Datasheet - Page 10

• Manufacturer Part Number: max5187beeg
• Description: 8-bit, 40mhz, Current/voltage-output Dacs
• Manufacturer: Maxim Integrated Products, Inc.

To disable the MAX5187/MAX5190’s internal reference,
connect REN to DV
erence may now be applied to drive the REFO pin to set
the full-scale output (Figure 3). Choose a reference that
can supply at least 150µA to drive the bias circuit that
generates the cascode current for the current array. For
improved accuracy and drift performance, choose a volt-
age reference with a fixed output voltage, such as the
+1.2V, 25ppm/°C MAX6520 bandgap reference.
To enter the lower power standby mode, connect the
digital inputs PD and DACEN to DGND. In standby,
both the reference and the control amplifier are active
with the current array inactive. To exit this condition,
DACEN must be pulled high with PD held at DGND.
Both the MAX5187 and MAX5190 typically require 50µs
to wake up and allow both the outputs and the refer-
ence to settle.
8-Bit, 40MHz, Current/Voltage-Output DACs
Table 1. Power-Down Mode Selection
X = Don’t care
10
Figure 4. Timing Diagram
(POWER-DOWN SELECT)
D0–D7
OUT
CLK
______________________________________________________________________________________
PD
0
0
1
t
DS
DD
. A temperature-stable external ref-
N - 1
(DAC ENABLE)
External Reference
DACEN
t
CLK
0
1
X
Standby Mode
N - 1
POWER-DOWN MODE
Shutdown
Wake-Up
Standby
N
For lowest power consumption, the MAX5187/MAX5190
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DAC’s supply current is reduced to 1µA. To enter this
mode, connect PD to DV
connect PD to DGND and DACEN to DV
are required for the parts to leave shutdown mode and
settle to their outputs’ values prior to shutdown.
Figure 4 shows a detailed timing diagram for the
MAX5187/MAX5190. With each high transition of the
clock, the input latch is loaded with the digital value set
by bits D7 through D0. The content of the input latch is
then shifted to the DAC register, and the output
updates at the rising edge of the next clock.
t
DH
N
t
CL
MAX5187
MAX5190
MAX5187
MAX5190
Last state prior to standby mode
DD
OUTPUT STATE
N + 1
. To return to active mode,
t
CH
Timing Information
Shutdown Mode
N + 1
DD
High-Z
High-Z
AGND
AGND
. About 50µs