max5235 Maxim Integrated Products, Inc., max5235 Datasheet - Page 12

• Manufacturer Part Number: max5235
• Description: Single-supply 3v/5v, Voltage-output, Dual, Precision 12-bit Dacs
• Manufacturer: Maxim Integrated Products, Inc.

register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the control bits and D11–D8. The maxi-
mum clock frequency guaranteed for proper operation
is 13.5MHz. Figure 2 depicts a more detailed timing
diagram of the serial interface.
As described in Tables 2 and 3, several serial interface
commands put one or both of the DACs into shutdown
mode. Shutdown modes are completely independent
for each DAC. In shutdown, the amplifier output
becomes high impedance, and OUT_ terminates to
GND through the 200kΩ (typ) gain resistors. Optionally
(see Tables 2 and 3), OUT_ can have a termination of
1kΩ to GND.
Full power-down mode shuts down the main bias gen-
erator and both DACs. The shutdown impedance of the
DAC outputs can still be controlled independently, as
described in Tables 2 and 3.
A serial interface command exits shutdown mode and
updates a DAC register. Each DAC can exit shutdown
at the same time or independently (see Tables 2 and
3). For example, if both DACs are shut down, updating
the DAC A register causes DAC A to power up, while
DAC B remains shut down. In full power-down mode,
powering up either DAC also powers up the main bias
generator. To change from full power-down to both
DACs shutdown mode requires the waking of at least
one DAC between states.
When powering up the MAX5234/MAX5235 (powering
V
output to stabilize. When exiting full power-down mode,
allow 60µs max (MAX5234) or 70µs max (MAX5235) for
the output to stabilize. When exiting DAC shutdown
mode, allow 50µs max (MAX5234) or 60µs max
(MAX5235) for the output to stablize.
Asserting LDAC asynchronously loads the DAC regis-
ters from their corresponding input registers (DACs that
are shut down remain shut down). The LDAC input is
totally asynchronous and does not require any activity
on CS, SCLK, or DIN in order to take effect. If LDAC is
asserted coincident with a rising edge of CS, which
executes a serial command modifying the value of
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
Table 1. Serial Data Format
12
DD
3 Control Bits
MSB
), allow 60µs (MAX5234) or 70µs (MAX5235) for the
C2...C0
______________________________________________________________________________________
<-----------
Power-Down and Shutdown Modes
MSB......12 Data Bits.....LSB
D11................................D0
16 bits of serial data
Load DAC Input ( LDAC )
----------->
Sub Bit
S0
LSB
either DAC input register, then LDAC must remain
asserted for at least 30ns following the CS rising edge.
This requirement applies only for serial commands that
modify the value of the DAC input registers.
Integral nonlinearity (Figure 6a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the endpoints of the transfer
function, once offset and gain errors have been nulli-
fied. For a DAC, the deviations are measured at every
single step.
Differential nonlinearity (Figure 6b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than 1LSB, the
DAC guarantees no missing codes and is monotonic.
The offset error (Figure 6c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
Gain error (Figure 6d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its new
output value within the converter’s specified accuracy.
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
layout and grounding significantly reduces this noise,
but there is always some feedthrough caused by the
DAC itself.
Figure 7 shows the MAX5234/MAX5235 configured for
unipolar, rail-to-rail operation with a gain of 1.6384V/V.
The MAX5235 produces a 0 to 4.095V output with 2.5V
reference while the MAX5234 produces a range of 0 to
Applications Information
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Digital Feedthrough
Unipolar Output
Settling Time
Definitions
Offset Error
Gain Error