max5811peut-t Maxim Integrated Products, Inc., max5811peut-t Datasheet - Page 9

• Manufacturer Part Number: max5811peut-t
• Description: Max5811 10-bit, Low-power, 2-wire Interface, Serial, Voltage-output Dac
• Manufacturer: Maxim Integrated Products, Inc.

low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure
the beginning of a transmission to the MAX5811. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see
Acknowledge Bit). The STOP condition frees the bus. If
a repeated START condition (Sr) is generated instead of
a STOP condition, the bus remains active. When a
STOP condition or incorrect address is detected, the
MAX5811 internally disconnects SCL from the serial
interface until the next START condition, minimizing digi-
tal noise and feedthrough.
The MAX5811 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition
This condition is not a legal I
clock pulse must separate any START and STOP condi-
tions.
A REPEATED START (S
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S
master is writing to several I
want to relinquish control of the bus. The MAX5811 ser-
ial interface supports continuous write operations with
or without an S
read operations require S
change in direction of data flow.
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5811 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5811 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7-
bit slave address
waits for a START condition followed by its slave
address. The serial interface compares each address
2). A START condition from the master signals
r
10-Bit Low Power 2-Wire Interface Serial,
condition separating them. Continuous
_______________________________________________________________________________________
(Figure
r
may also be used when the bus
Repeated START Conditions
r
) condition may indicate a
4). When idle, the MAX5811
r
conditions because of the
2
C devices and does not
Acknowledge Bit (ACK)
Early STOP Conditions
2
C format; at least one
Slave Address
(Figure
3).
value bit by bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the
R/W indicates whether the master is writing to or read-
ing from the MAX5811 (R/W = 0 selects the write condi-
tion, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5811 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5811 has eight different factory/user-pro-
grammed addresses
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to V
MAX5811s to share the same bus.
In write mode (R/W = 0), data that follows the address
byte controls the MAX5811
figure the MAX5811
data. Bits S1 and S0 are sub-bits and are always zero.
Input and DAC registers update on the falling edge of
SCL during the acknowledge bit. Should the write cycle
be prematurely aborted, data is not updated and the
Table 2. MAX5811 I
Figure 4. Slave Address Byte Definition
Figure 5. Command Byte Definition
DD
MAX5811M
MAX5811M
MAX5811N
MAX5811N
MAX5811L
MAX5811L
MAX5811P
MAX5811P
PART
Voltage-Output DAC
S
sets A0 = 1. This feature allows up to eight
C3
A6
C2
A5
C1
A4
(Table
C0
(Table
V
GND
GND
GND
GND
2
V
V
V
V
ADD
C Slave Addresses
DD
DD
DD
DD
A3
(Figure
D9
3). Bits D9–D0 are DAC
A2
2). Address bits A6
Read/Write (R/W) bit.
D8
5). Bits C3–C0 con-
Write Data Format
DEVICE ADDRESS
A1
D7
0010 000
0010 001
0010 010
0010 011
0110 100
0110 101
1010 100
1010 101
(A
A0
6
...A
D6
R/W
0
)
9