ds8007-skt Maxim Integrated Products, Inc., ds8007-skt Datasheet
ds8007-skt
Related parts for ds8007-skt
ds8007-skt Summary of contents
Page 1
... Rev 1; 10/07 Multiprotocol Dual Smart Card Interface General Description The DS8007 multiprotocol dual smart card interface is a low-cost, dual smart card reader interface supporting all ISO 7816, EMV™, and GSM11-11 requirements. Through its 8-bit parallel bus and dedicated address selects (AD3–AD0), the DS8007 can easily and directly connect to the nonmultiplexed byte-wide bus of a Maxim/Dallas secure microcontroller ...
Page 2
Multiprotocol Dual Smart Card Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on V Relative to Ground ...........-0.5V to +6.5V DD Voltage Range on V Relative to Ground .........-0.5V to +6.5V DDA Voltage Range on Any Pin Relative to Ground Pins CPA1, ...
Page 3
Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued +3.3V +3.3V +25°C, unless otherwise noted.) (Note 1) DD DDA A PARAMETER SYMBOL Alarm Pulse Width External Clock Frequency Internal Oscillator Voltage on V Pin UP ...
Page 4
Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued +3.3V +3.3V +25°C, unless otherwise noted.) (Note 1) DD DDA A PARAMETER SYMBOL Output Low Card Voltage Inactive Mode Output Current Output Low Voltage V CCx ...
Page 5
Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued +3.3V +3.3V +25°C, unless otherwise noted.) (Note 1) DD DDA A PARAMETER SYMBOL Output Low V Voltage Card Inactive Output Current I Mode Internal Pullup R ...
Page 6
Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued +3.3V +3.3V +25°C, unless otherwise noted.) (Note 1) DD DDA A PARAMETER SYMBOL Input Low Voltage V Input High Voltage V Input Low Current I Input ...
Page 7
Multiprotocol Dual Smart Card Interface AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR MULTIPLEXED PARALLEL BUS (V = 3.3V 3.3V +25°C, unless otherwise noted.) (Figure 1) DD DDA A PARAMETER SYMBOL XTAL 1 Cycle Time t CY(XTAL1) ALE Pulse ...
Page 8
Multiprotocol Dual Smart Card Interface AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR NONMULTIPLEXED PARALLEL BUS (READ AND WRITE 3.3V 3.3V +25°C, unless otherwise noted.) (See Figure 2.) DD DDA A PARAMETER RD High to CS Low ...
Page 9
Multiprotocol Dual Smart Card Interface AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR CONSECUTIVE READ/WRITE TO URR/UTR/TOC (V = 3.3V 3.3V +25°C, unless otherwise noted.) DD DDA A PARAMETER SYMBOL SEE FIGURE 3 RD Pulse Width t RD Low ...
Page 10
Multiprotocol Dual Smart Card Interface I/Ox TBE BIT INT WR/CS t W(WR) t CRED BIT WR(UTR) Figure 4. Timing Between Two Write Operations in Register UTR t WR/CS W(WR) t CRED BIT WR(TOC) Figure 5. Timing Between Two Write Operations ...
Page 11
Multiprotocol Dual Smart Card Interface PIN NAME Reset Output. This active-high output is provided for resetting external devices. The RSTOUT pin is driven 1 RSTOUT high until the DELAY pin reaches V it can externally be pulled down. The SUPL ...
Page 12
... CS and WR are low. Active-Low Parallel Bus Write Strobe Input. In multiplexed mode, this input indicates when the host processor writing information to the DS8007. In nonmultiplexed mode, a low on this pin signals the bus is engaged in a read or write operation Active-Low Chip-Select Input ...
Page 13
... V UP Figure 6. Block Diagram no edge (activity) is detected on the ALE pin. Once a rising edge is detected on the ALE pin, the DS8007 is placed into the multiplexed mode of operation. Once in the multiplexed mode of operation, a reset/power cycle or the deassertion of CS forces the device to the non- multiplexed mode. Connecting the ALE pin to V ground forces the device into nonmultiplexed parallel bus mode ...
Page 14
... RD and WR strobe input signals are used to enable a read or write operation, respectively, if the DS8007 is selected (i.e 0). See the AC timing for the multiplexed parallel bus mode found earlier in this data sheet. 14 ...
Page 15
... Control Registers Special control registers that the host computer/micro- controller accesses through the parallel bus manage most DS8007 features. Many of the registers, although only mentioned once in the listing, are duplicated for each card interface. The PDR, GTR, UCR1, UCR2, and CCR registers exist separately for each of the three card interfaces ...
Page 16
... Bits Identification Bits (CSR7 to CSR4). These bits provide a method for software to identify the device as follows: 0011 = DS8007 revision Ax Bit 3: Reset ISO UART (RIU). When this bit is cleared (0), most of the ISO UART registers are reset to their initial values. This bit must be cleared for at least 10ns prior to initiating an activation sequence ...
Page 17
Multiprotocol Dual Smart Card Interface 7 6 Address 02h PD7 PD6 RW-0 RW unrestricted read unrestricted write value after reset; all bits unaffected by RIU = 0. Bits Programmable ETU Divider ...
Page 18
... Insertion of card A or card B (detected by PRLA or PRLB). • Withdrawal of card A or card B (detected by PRLA or PRLB). • Reassertion of the CS pin to select the DS8007 (CS must be deasserted after setting PDWN = 1 for this event to exit from power-down). • INTAUXL bit is set due to change in INTAUX (INTAUXL bit must be cleared first). • ...
Page 19
Multiprotocol Dual Smart Card Interface 7 6 Address 06h FTE0 FIP R-0 RW unrestricted read unrestricted write value after reset. This register is reset to 0uuu00uub on RIU = 0. Bit 7: FIFO Threshold ...
Page 20
Multiprotocol Dual Smart Card Interface 7 6 Address 07h — — R-0 R unrestricted read unrestricted write value after reset. This register is reset to 0011uuuub on RIU = 0. Note: The AUX card ...
Page 21
Multiprotocol Dual Smart Card Interface 7 6 Address 09h TOL7 TOL6 W-0 W unrestricted read unrestricted write value after reset. This register is unchanged on RIU = 0. Bits Timeout Counter ...
Page 22
... Bit 4: Control Ready (CRED). This bit signals the host device that the DS8007 is ready to handle the next write operation to UTR or TOC or the next read opera- tion of URR. When CRED = 0, the DS8007 is still work- ing on the previous operation and cannot correctly process the new read/write request. When CRED = 1, the DS8007 is ready for the next read/write request. This “ ...
Page 23
... PE bit is set indicate that the par- ity error limit has been reached. In transmit mode, the DS8007 attempts to retransmit a character up to (PEC2–PEC0) times (when NAK’d by the card) before the PE bit is set. Retransmission attempts are automati- cally made at 15 ETU from the previous start bit. If PEC2– ...
Page 24
Multiprotocol Dual Smart Card Interface 7 6 Address 0Eh TO3 TO2 R-0 R unrestricted read unrestricted write value after reset. All register bits are reset to 00000000b on RIU = 0. Note: If any ...
Page 25
Multiprotocol Dual Smart Card Interface 7 6 Address 0Fh — PRTLB R-0 R unrestricted read unrestricted write value after reset always reflects state of external device pin. This register is reset to ...
Page 26
... The DELAY pin is an external indicator of the state of internal power and can also be driven external hold the device in a reset state. An external capac- itor is usually attached to this pin, defining the time constant of a power-on delay for the DS8007. When V is below the voltage threshold V DD ...
Page 27
Multiprotocol Dual Smart Card Interface V = 2.1V TO 2.5V RST ~1.25V DRST DELAY RSTOUT INT SUPL BIT Figure 8. Voltage Supervisor RESULTING FROM SUPL BIT CLEARED BY HSR READ ONLY ____________________________________________________________________ ...
Page 28
Multiprotocol Dual Smart Card Interface Activation Sequencing An activation sequence can only be requested by a host device through the parallel bus interface. The host can request an activation sequence for a specific card (card A or card B) by ...
Page 29
Multiprotocol Dual Smart Card Interface Deactivation Sequencing The host device can request a deactivation sequence by resetting the START bit to 0 for the desired card interface. The deactivation (from the deassertion of the START bit, step 1 of the ...
Page 30
Multiprotocol Dual Smart Card Interface Timeout Counter Operation The timeout counter assists the host device in timing real-time events associated with the communication pro- tocols: the Work Wait Time (WWT), Block Waiting Time (BWT), etc. The timeout counter registers count ...
Page 31
Multiprotocol Dual Smart Card Interface Table 3. Timeout Counter Configurations (continued) TOC VALUE TOR3 TOR2 71h Start Bit 75h Start Bit 7Ch Start Bit 85h Stopped E5h Software Start Bit/Autostop F1h (RCV); Start Bit (XMT) Start Bit/Autostop F5h (RCV); Start ...
Page 32
Multiprotocol Dual Smart Card Interface ISO UART Implementation The HSR.RIU control bit resets the ISO UART. The HSR.RIU must be reset prior to any activation. HSR.RIU must be returned software before any UART action can take place. ...
Page 33
... RSTx START BIT Figure 11. ETU Generation Standard Clock Frequencies The DS8007 supports I/O communication and CLKx frequency generation compliant to the following stan- dards: ISO 7816, EMV2000, and GSM11-11. Each of these standards has an allowable CLKx frequency range and a defined relationship between CLKx fre- quency and ETU (baud rate) generation that is support- ed initially and after negotiation ...
Page 34
Multiprotocol Dual Smart Card Interface tinue to be used until a successful PPS exchange is completed. The negotiated Fn, Dn values are then used after a successful PPS exchange. If the card comes up in specific mode (i.e., TA(2) is ...
Page 35
... protocol. The AUTOC bit should not be modified during a card session. Framing Error Detection The DS8007 monitors the selected card I/Ox signal at 10.25 ETU following each detected start bit. If the I/Ox signal is not in the high state at this point in time, the USR ...
Page 36
... UTR register. Some smart cards require extra time to handle informa- tion received from an interface device. To allow this extra time, the DS8007 implements a Guard Time Register (GTR) per card interface. This register is pro- grammed with the number of extra ETU that should be ...
Page 37
... ISO UART tests for correct parity on each received character. If UCR1.FIP is configured to 1, inverse parity is expected. This control can be useful in testing that the ICC prop- erly detects error signals generated by the DS8007 and retransmits requested characters. LAST CHARACTER TO TRANSMIT LCT BIT WRITTEN SOFTWARE, THEN LOAD UTR ...
Page 38
... Configuring PEC2–PEC0 bits to 001b means one repe- tition in reception is allowed and that the DS8007 gen- erates an error signal only once per character receive attempt. When the consecutive parity error counter ...
Page 39
... I/O line begins between 400 and 40,000 clock cycles after the rising edge of the RSTx signal. Development and Technical The DS8007 evaluation kit (EV kit) is available to assist in the development of designs using the DS8007 multi- protocol smart card interface. The EV kit can be pur- chased directly from Maxim/Dallas Semiconductor ...
Page 40
Multiprotocol Dual Smart Card Interface 40 ____________________________________________________________________ Typical Operating Circuit ...
Page 41
... Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 41 © 2007 Maxim Integrated Products is a registered trademark of Dallas Semiconductor Corporation. Pages changed at Rev 1: 1, 40, 41 56-G4021-001 is a registered trademark of Maxim Integrated Products, Inc. Revision History ...