adcs9888cvh-205 National Semiconductor Corporation, adcs9888cvh-205 Datasheet - Page 6

• Manufacturer Part Number: adcs9888cvh-205
• Description: 205/170/140 Msps Video Analog Front End
• Manufacturer: National Semiconductor Corporation

www.national.com
Pin Descriptions
Data Clock Output
123
124
Data Outputs
113-120
103-110
90-97
80-87
70-77
57-64
Voltage Reference Bypass
2
9
24
PLL Loop Filter
50
Pin
DATACK
DATACK_B Digital
D
D
D
D
D
D
REF
BYPASS
R
(NC)
B
(NC)
FILT
MIDSC
R
R
G
G
B
B
MIDSC
_A(7:0)
_B(7:0)
_A(7:0)
_B(7:0)
_A(7:0)
_B(7:0)
Label
V
V
(Continued)
Digital
Output
Output
Digital
Output
Digital
Output
Digital
Output
Digital
Output
Digital
Output
Digital
Output
Analog
Bypass
Analog
Bypass
Analog
Bypass
PLL VCO
Bypass
Type
Data Output Clock. Complementary data clocks are provided so that output
data and HSOUT can be synchronously captured by external logic or
memory devices. The clock outputs are synchronous with the internal pixel
sample clock. As the sampling phase is adjusted, the DATACK, data, and
HSOUT signals all shift together with the sampling interval. When the chip
is in power down or seek mode, the DATACK outputs enter a high
impedance state.
Data Output Clock Invert. See DATACK description.
Red Port A (V or U/V) Output Data. Converted pixel data is presented at
the data output port synchronous with the DATACK and HSOUT signals.
As the pixel sample phase is adjusted, the HSOUT, DATACK and data
outputs all shift together. In single channel mode, all data is presented at
the A output ports. In dual channel mode, output data is presented at A
and B outputs, either in alternating (interleaved mode) or simultaneous
(parallel mode ) timing. When 4:2:2 pulldown mode is enabled, only the A
ports are used, with U/V data output on Red Port A, and Y data output on
Green Port A. When the chip is in seek mode, or low power mode, all data
outputs are placed in a high impedance state. See the applications section
and configuration registers section for more information.
Red Port B (V) Output Data. See D
Green Port A (Y) Output Data. See D
Green Port B (Y) Output Datasheet. See D
Blue Port A (U) Output Data. See D
Blue Port B (U) Output Data. See D
Internal Reference Bypass. A 0.1 µF capacitor will be connected from this
pin to ground, to provide a low impedance decoupling for the internal
1.23V bandgap voltage reference.
Red (V) Channel midscale Voltage Bypass. No external bypass is required
for the midscale voltage. Therefore, this pin is not connected to the internal
circuitry. To maintain compatibility with other designs external capacitors
can be connected without affecting operation, performance, or reliability.
Blue (U) Channel midscale Voltage Bypass. No external bypass is required
for the midscale voltage. Therefore, this pin is not connected to the internal
circuitry. To maintain compatibility with other designs external capacitors
can be connected without affecting operation, performance, or reliability.
Phase Locked Loop - Voltage Controlled Oscillator filter connection. An
R/C filter circuit is used to maintain the VCO control voltage. This circuit
should be isolated from all other circuitry to minimize clock jitter. The circuit
is connected to the PV
power and ground buses. Refer to the applications section for more
information.
6
D
bus to provide the maximum isolation from noisy
Description
R
R
R
_A(7:0).
_A(7:0).
_A(7:0).
R
_A(7:0).
R
_A(7:0).