adc12041 National Semiconductor Corporation, adc12041 Datasheet - Page 20

• Manufacturer Part Number: adc12041
• Description: 12-bit Plus Sign 216 Khz Sampling Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
b
0
0
0
0
1
7
Register Bit Description
b
Acquisition Time section, page 22).
b
sion results will appear as a code of zero in the Data register. The SE bit is cleared at power-up.
b
D
16-bit data bus and data pins D
b
mode. In this mode a rising edge on the SYNC pin causes the ADC to hold the input signal and begin a conversion. When b
a ’0’, the SYNC pin is programmed as an output and the converter is in an asynchronous mode. In this mode the signal at the
SYNC pin indicates the status of the converter. The SYNC pin is high when a conversion is taking place. The SYNC bit is set at
power-up .
b
DATA REGISTER (Read Only)
This is a 13-bit read only register that holds the 12-bit + sign conversion result in two’s complement form. All reads performed from
the ADC12041 will place the contents of this register on the data bus. When reading the data register in 8-bit mode, the sign bit
is extended.
Power on State: 0000Hex
b
b
Functional Description
The ADC12041 is programmed through a digital interface
that supports an 8-bit or 16-bit data bus. The digital interface
consists of a 13-bit data input/output bus (D
control signals and two internal registers: a write only 8-bit
Configuration register and a read only 13-bit Data register.
The Configuration register programs the functionality of the
ADC12041. The 8 bits of the Configuration register are di-
vided into 5 fields. Each field controls a specific function of
the ADC12041: the acquisition time, synchronous or asyn-
chronous conversions, mode of operation and the data bus
size.
1
2
3
4
7
11
12
7
MSB
–b
: When the Single-Ended bit (SE bit) is a ’1’, conversion results will be limited to positive values only and any negative conver-
: This is the Bus Width (BW) bit. When this bit is a ’0’ the ADC12041 is configured to interface with an 8-bit data bus; data pins
: The SYNC bit. When the SYNC bit is a ’1’, the SYNC pin is programmed as an input and the converter is in synchronous
–b
sign
–D
b
b
–b
: This bit contains the sign of the conversion result. 0 for positive results and 1 for negative.
12
0
0
1
1
0
6
0
5
b
0
0
: The ACQ TIME bits select one of four possible acquistion times in the SYNC-OUT mode (b
: The command field. These bits select the mode of operation of the ADC12041. Power-up value is 000. (See Note 22)
0
0
1
1
: b
1
are active and pins D
b
11
0
1
0
1
0
5
b
is the most significant bit and b
11
Standby command. This puts the ADC in a low power consumption mode.
Ful-Cal command. This will cause the ADC to perform a self-calibrating cycle that will correct linearity and zero
errors.
Auto-zero command. This will cause the ADC to perform an auto-zero cycle that corrects offset errors.
Reset command. This puts the ADC in an idle mode.
Start command. This will put the converter in a start mode, preparing it to perform a conversion. If in
asynchronous mode (b
ended. In synchronous mode (b
b
0
1
0
1
b
0
10
12
b
–D
9
12
9
–D
Clocks
are in TRI-STATE. When the BW bit is a ’1’, the ADC12041 is configured to interface with a
0
15
47
79
b
9
are all active. The BW bit is cleared at power-up.
8
4
= “0”), conversions will immediately begin after the programmed acquisition time has
(Continued)
0
b
is the least significant bit of the conversion result.
12
7
–D
4
Conversion Data
= “1”), conversions will begin after a rising edge appears on the SYNC pin.
0
), digital
b
6
b
5
20
Command
Features and Operating Modes
SELECTABLE BUS WIDTH
The ADC12041 can be programmed to interface with an 8-bit
or 16-bit data bus. The BW bit (b
ister controls the bus size. The bus width is set to 8 bits
(D
bit is cleared or 13 bits (D
set. At power-up the default bus width is 8 bits (BW = 0).
In 8-bit mode the Configuration register is accessed with a
single write. When reading the ADC in 8-bit mode, the first
read cycle places the lower byte of the Data register on the
data bus followed by the upper byte during the next read
cycle.
In 13-bit mode all bits of the Data register and Configuration
register are accessible with a single read or write cycle.
b
7
4
–D
0
are active and D
b
3
b
2
b
12
1
12
–D
–D
8
are in TRI-STATE) if the BW
0
4
LSB
b
3
are active) if the BW bit is
= 0). (Refer to Selectable
) in the Configuration reg-
0
8
is