adc12d1000/1600ciut/nopb National Semiconductor Corporation, adc12d1000/1600ciut/nopb Datasheet - Page 48

• Manufacturer Part Number: adc12d1000/1600ciut/nopb
• Description: Adc12d1000/adc12d1600 12-bit, 2.0/3.2 Gsps Ultra High-speed Adc
• Manufacturer: National Semiconductor Corporation

www.national.com
17.3.2.2 LVDS Output Differential Voltage
The ADC12D1000/1600 is available with a selectable higher
or lower LVDS output differential voltage. This parameter is
V
be selected via the OVS Bit (Addr: 0h, Bit 13). For many ap-
plications, in which the LVDS outputs are very close to an
FPGA on the same board, for example, the lower setting is
sufficient for good performance; this will also reduce the pos-
sibility for EMI from the LVDS outputs to other signals on the
board. See
mation.
17.3.2.3 LVDS Output Common-Mode Voltage
The ADC12D1000/1600 is available with a selectable higher
or lower LVDS output common-mode voltage. This parameter
is V
LVDS Output Common-mode Pin (V
how to select the desired voltage.
17.3.2.4 Output Formatting
The formatting at the digital data outputs may be either offset
binary or two's complement. The default formatting is offset
binary, but two's complement may be selected via the 2SC
Bit (Addr: 0h, Bit 4); see
more information.
17.3.2.5 Demux/Non-demux Mode
The ADC12D1000/1600 may be in one of two demultiplex
modes: Demux Mode or Non-Demux Mode (also sometimes
referred to as 1:1 Demux Mode). In Non-Demux Mode, the
data from the input is simply output at the sampling rate on
one 12-bit bus. In Demux Mode, the data from the input is
output at half the sampling rate, on twice the number of buses.
Demux/Non-Demux Mode may only be selected by the NDM
pin. In Non-DES Mode, the output data from each channel
may be demultiplexed by a factor of 1:2 (1:2 Demux Non-DES
Mode) or not demultiplexed (Non-Demux Non-DES Mode). In
DES Mode, the output data from both channels interleaved
may be demultiplexed (1:4 Demux DES Mode) or not demul-
tiplexed (Non-Demux DES Mode).
17.3.2.6 Test Pattern Mode
The ADC12D1000/1600 can provide a test pattern at the four
output buses independently of the input signal to aid in system
debug. In Test Pattern Mode, the ADC is disengaged and a
test pattern generator is connected to the outputs, including
ORI and ORQ. The test pattern output is the same in DES
Mode or Non-DES Mode. Each port is given a unique 12-bit
word, alternating between 1's and 0's. When the part is pro-
grammed into the Demux Mode, the test pattern’s order is
described in
the test pattern will not be output for that channel.
OD
FIGURE 13. DDR DCLK-to-Data Phase Relationship
OS
and may be found in
and may be found in
Section 19.0 Register Definitions
Table
21. If the I- or Q-channel is powered down,
Section 19.0 Register Definitions
Table
Table
12. The desired voltage may
12. See
BG
)
for information on
Section 17.2.1.11
for more infor-
30091694
for
48
When the part is programmed into the Non-Demux Mode, the
test pattern’s order is described in
17.3.2.7 Time Stamp
The Time Stamp feature enables the user to capture the tim-
ing of an external trigger event, relative to the sampled signal.
When enabled via the TSE Bit (Addr: 0h; Bit: 3), the LSB of
the digital outputs (DQd, DQ, DId, DI) captures the trigger in-
formation. In effect, the 12-bit converter becomes an 11-bit
converter and the LSB acts as a 1-bit converter with the same
latency as the 11-bit converter. The trigger should be applied
to the DCLK_RST input. It may be asynchronous to the ADC
sampling clock.
17.3.3 Calibration Feature
The ADC12D1000/1600 calibration must be run to achieve
specified performance. The calibration procedure is exactly
the same regardless of how it was initiated or when it is run.
Calibration trims the analog input differential termination re-
sistors, the CLK input resistor, and sets internal bias currents
which affect the linearity of the converter. This minimizes full-
Time
T10 000h 004h 008h 010h
T11 FFFh FFBh FF7h FEFh
T12 000h 004h 008h 010h
T13
Time
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
FFFh FFBh FF7h FEFh
FFFh FFBh FF7h FEFh
FFFh FFBh FF7h FEFh
FFFh FFBh FF7h FEFh
000h 004h 008h 010h
000h 004h 008h 010h
000h 004h 008h 010h
000h 004h 008h 010h
000h 004h 008h 010h
000h 004h 008h 010h
TABLE 21. Test Pattern by Output Port in
TABLE 22. Test Pattern by Output Port in
Qd
...
FFFh
FFFh
FFFh
FFFh
FFFh
FFFh
FFFh
FFFh
000h
000h
000h
000h
000h
000h
...
Q
Id
...
FFBh
FFBh
FFBh
FFBh
FFBh
FFBh
FFBh
FFBh
004h
004h
004h
004h
004h
004h
Non-Demux Mode
...
I
...
Q
Demux Mode
ORQ
...
I
0b
0b
1b
1b
0b
1b
0b
1b
1b
1b
0b
0b
1b
1b
...
ORQ ORI Comments
Table
0b
1b
0b
1b
0b
0b
1b
0b
1b
0b
0b
1b
0b
...
ORI
0b
0b
1b
1b
0b
1b
0b
1b
1b
1b
0b
0b
1b
1b
...
22.
0b
1b
0b
1b
0b
0b
1b
0b
1b
0b
0b
1b
0b
...
Comments
Sequence
Sequence
Sequence
Sequence
Sequence
Pattern
Pattern
Pattern
Pattern
Pattern
n+1
n
n+1
n+2
n