adc12d1000/1600ciut/nopb National Semiconductor Corporation, adc12d1000/1600ciut/nopb Datasheet - Page 52

• Manufacturer Part Number: adc12d1000/1600ciut/nopb
• Description: Adc12d1000/adc12d1600 12-bit, 2.0/3.2 Gsps Ultra High-speed Adc
• Manufacturer: National Semiconductor Corporation

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18.1.3 FSR and the Reference Voltage
The full-scale analog differential input range (V
ADC12D1000/1600 is derived from an internal bandgap ref-
erence. In Non-ECM, this full-scale range has two settings
controlled by the FSR Pin; see
Input Range Pin
Q-channels. In ECM, the full-scale range may be indepen-
dently set for each channel via Addr:3h and Bh with 15 bits
of precision; see
SNR is obtained with a higher full-scale input range, but better
distortion and SFDR are obtained with a lower full-scale input
range. It is not possible to use an external analog reference
voltage to modify the full-scale range, and this adjustment
should only be done digitally, as described.
A buffered version of the internal bandgap reference voltage
is made available at the V
drive a load of up to 80 pF and source or sink up to 100 μA.
It should be buffered if more current than this is required. This
pin remains as a constant reference voltage regardless of
what full-scale range is selected and may be used for a sys-
tem reference. V
used to select a higher LVDS output common-mode voltage;
see
(V
18.1.4 Out-Of-Range Indication
Differential input signals are digitized to 12 bits, based on the
full-scale range. Signal excursions beyond the full-scale
range, i.e. greater than +V
be clipped at the output. An input signal which is above the
FSR will result in all 1's at the output and an input signal which
is below the FSR will result in all 0's at the output. When the
conversion result is clipped for the I-channel input, the Out-
of-Range I-channel (ORI) output is activated such that ORI+
goes high and ORI- goes low while the signal is out of range.
This output is active as long as accurate data on either or both
of the buses would be outside the range of 000h to FFFh. The
Q-channel has a separate ORQ which functions similarly.
18.1.5 Maximum Input Range
The recommended operating and absolute maximum input
range may be found in
Section 10.0 Absolute Maximum
the stated allowed operating conditions, each Vin+ and Vin-
input pin may be operated in the range from 0V to 2.15V if the
input is a continuous 100% duty cycle signal and from 0V to
2.5V if the input is a 10% duty cycle signal. The absolute
maximum input range for Vin+ and Vin- is from -0.15V to 2.5V.
These limits apply only for input signals for which the input
common mode voltage is properly maintained.
18.1.6 AC-coupled Input Signals
The ADC12D1000/1600 analog inputs require a precise com-
mon-mode voltage. This voltage is generated on-chip when
AC-coupling Mode is selected. See
DC-Coupled Mode Pin (V
to select AC-coupled Mode.
In AC-coupled Mode, the analog inputs must of course be AC-
coupled. For an ADC12D1000/1600 used in a typical appli-
cation, this may be accomplished by on-board capacitors, as
shown in
inputs on the Reference Board are directly connected to the
analog inputs on the ADC12D1000/1600, so this may be ac-
complished by DC blocks (included with the hardware kit).
When the AC-coupled Mode is selected, an analog input
channel that is not used (e.g. in DES Mode) should be con-
BG
).
Section 17.2.1.11 LVDS Output Common-mode Pin
Figure
15. For the ADC12D1000/1600RB, the SMA
(FSR). The FSR Pin operates on both I- and
BG
Section 19.0 Register
is a dual-purpose pin and it may also be
Section 11.0 Operating Ratings
CMO
BG
IN_FSR
Pin for the user. The V
)
for more information about how
/2 or less than -V
Ratings, respectively. Under
Section 17.2.1.9 Full-Scale
Section 17.2.1.10 AC/
Definitions. The best
IN_FSR
IN_FSR
BG
) of the
pin can
/2, will
and
52
nected to AC ground, e.g. through capacitors to ground . Do
not connect an unused analog input directly to ground.
The analog inputs for the ADC12D1000/1600 are internally
buffered, which simplifies the task of driving these inputs and
the RC pole which is generally used at sampling ADC inputs
is not required. If the user desires to place an amplifier circuit
before the ADC, care should be taken to choose an amplifier
with adequate noise and distortion performance, and ade-
quate gain at the frequencies used for the application.
18.1.7 DC-coupled Input Signals
In DC-coupled Mode, the ADC12D1000/1600 differential in-
puts must have the correct common-mode voltage. This volt-
age is provided by the device itself at the V
is recommended to use this voltage because the V
potential will change with temperature and the common-mode
voltage of the driving device should track this change. Full-
scale distortion performance falls off as the input common
mode voltage deviates from V
mended to keep the input common-mode voltage within 100
mV of V
±150 mV (maximum). See V
V
in AC- and DC-coupled Mode are similar, provided that the
input common mode voltage at both analog inputs remains
within 100 mV of V
18.1.8 Single-Ended Input Signals
The analog inputs of the ADC12D1000/1600 are not designed
to accept single-ended signals. The best way to handle sin-
gle-ended signals is to first convert them to differential signals
before presenting them to the ADC. The easiest way to ac-
complish single-ended to differential signal conversion is with
an appropriate balun-transformer, as shown in
When selecting a balun, it is important to understand the input
architecture of the ADC. The impedance of the analog source
should be matched to the ADC12D1000/1600's on-chip
CMI
FIGURE 16. Single-Ended to Differential Conversion
in
Section 16.0 Typical Performance Plots
CMO
FIGURE 15. AC-coupled Differential Input
(typical), although this range may be extended to
CMO
.
Using a Balun
CMI
CMO
in
. Therefore, it is recom-
Table 8
30091644
CMO
and ENOB vs.
. Performance
Figure
output pin. It
CMO
30091643
16.
output