adc12l032 National Semiconductor Corporation, adc12l032 Datasheet - Page 30

• Manufacturer Part Number: adc12l032
• Description: 3.3v Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Information
8.0 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion
errors. Input filtering can be used to reduce the effects of the
noise sources.
9.0 POWER SUPPLIES
Noise spikes on the V
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The
minimum power supply bypassing capacitors recommended
are low inductance tantalum capacitors of 10 µF or greater
paralleled with 0.1 µF monolithic ceramic capacitors. More or
different bypassing may be necessary depending on the
overall system requirements. Separate bypass capacitors
should be used for the V
close as possible to these pins.
10.0 GROUNDING
The ADC12L030/2/4/8’s performance can be maximized
through proper grounding techniques. These include the use
of separate analog and digital areas of the board with analog
and digital components and traces located only in their re-
spective areas. Bypass capacitors of 0.01 µF and 0.1 µF
surface mount capacitors and a 10 µF are recommended at
each of the power supply pins for best performance. These
capacitors should be located as close to the bypassed pin as
practical, especially the smaller value capacitors.
11.0 CLOCK SIGNAL LINE ISOLATION
The ADC12L030/2/4/8’s performance is optimized by routing
the analog input/output and reference signal conductors as
far as possible from the conductors that carry the clock
signals to the CCLK and SCLK pins. Maintaining a separa-
tion of at least 7 to 10 times the height of the clock trace
above its reference plane is recommended.
12.0 THE CALIBRATION CYCLE
A calibration cycle needs to be started after the power sup-
plies, reference, and clock have been given enough time to
stabilize after initial turn on. During the calibration cycle,
correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale,
offset, and linearity errors down to the specified limits. Full-
scale error typically changes
and linearity error changes even less; therefore it should be
necessary to go through the calibration cycle only once after
power up if the Power Supply Voltage and the ambient
temperature do not change significantly (see the curves in
the Typical Performance Characteristics).
13.0 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the A/D,
the auto-zero cycle can be used. It may be necessary to do
an auto-zero cycle whenever the ambient temperature or the
A
+
A
+
and V
and V
±
0.4 LSB over temperature
D
D
+
+
supply lines can cause
supplies and placed as
(Continued)
30
power supply voltage change significantly. (See the curves
titled “Zero Error Change vs. Ambient Temperature” and
“Zero Error Change vs. Supply Voltage” in the Typical Per-
formance Characteristics.)
14.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but the standard DC integral and differential nonlin-
earity specifications will not accurately predict the A/D con-
verter’s performance with AC input signals. The important
specifications for AC applications reflect the converter’s abil-
ity to digitize AC signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal-to-noise (S/N), signal-to-noise
+ distortion ratio (S/(N + D)), effective bits, full power band-
width, aperture time and aperture jitter are quantitative mea-
sures of the A/D converter’s capability.
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal wave-
form is applied to the A/D converter’s input, and the trans-
form is then performed on the digitized waveform. S/(N + D)
and S/N are calculated from the resulting FFT data, and a
spectral plot may also be obtained. Typical values for S/N
are shown in the table of Electrical Characteristics, and
spectral plots of S/(N + D) are included in the typical perfor-
mance curves..
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can be
seen in the S/(N + D) versus frequency curves. These curves
will also give an indication of the full power bandwidth (the
frequency at which the S/(N + D) or S/N drops 3 dB).
Effective number of bits can also be useful in describing the
A/D’s noise and distortion performance. An ideal A/D con-
verter will have some amount of quantization noise, deter-
mined by its resolution, and no distortion, which will yield an
optimum S/(N + D) ratio given by the following equation:
where "n" is the A/D’s resolution in bits.
Since the ideal A/D converter has no distortion, the effective
bits of a real A/D converter, therefore, can be found by::
As an example, this device with a
input signal will typically have a S/N of 78 dB, which is
equivalent to 12.6 effective bits.
15.0 AN RS232 SERIAL INTERFACE
Shown below is a schematic for an RS232 interface to any
IBM and compatible PCs. The DTR, RTS, and CTS RS232
signal lines are buffered via level translators and connected
to the ADC12L038’s DI, SCLK, and DO pins, respectively.
The D flip flop drive the CS control line.
n(effective) = ENOB = (S/(N + D) - 1.76 / 6.02
S/(N + D) = (6.02 x n + 1.76) dB
±
2.5V, 10 kHz sine wave