ad1836acsrl Analog Devices, Inc., ad1836acsrl Datasheet - Page 19
ad1836acsrl
Manufacturer Part Number
ad1836acsrl
Description
Multichannel 96 Khz Codec
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD1836ACSRL.pdf
(24 pages)
SPI CONTROL REGISTERS
Note that all control registers default to zero at power-up.
Table 12. Serial SPI Word Format
Register Address
15:12
4 Bits
Table 13. Register Addresses and Functions
Register Address
Bit 15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 14. DAC Control Register 1
Packed Mode: Eight channels are “packed” in DSDATA1 serial input. Packed Mode 128: Refer to Figure 7. Packed Mode 256: Refer to Figure 8.
Address
15, 14, 13, 12
0000
Bit 14
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
11
0
RD/WR
Bit 13
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Reserved
10
0
Bit 12
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
De-emphasis
9, 8
00 = None
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
Read/Write
11
1 = Read
0 = Write
RD/WR
Bit 11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Serial Mode
7, 6, 5
000 = I
001 = RJ
010 = DSP
011 = LJ
100 = Packed Mode 256
101 = Packed Mode 128
110 = Reserved
111 = Reserved
Rev. 0 | Page 19 of 24
2
S
Reserved
Bit 10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
10
0
Data-Word
Width
4, 3
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
Function
Bits 9:0
DAC Control 1
DAC Control 2
DAC1L Volume
DAC1R Volume
DAC2L Volume
DAC2R Volume
DAC3L Volume
DAC3R Volume
ADC1L—Peak Level (Read-Only)
ADC1R—Peak Level (Read-Only)
ADC2L—Peak Level (Read-Only)
ADC2R—Peak Level (Read-Only)
ADC Control 1
ADC Control 2
ADC Control 3
Reserved
Power-Down
2
0 = Normal
1 = PWRDWN
Data Field
9:0
10 Bits
Interpolator
Mode
1
0 = 8× (48 kHz)
1 = 4× (96 kHz)
AD1836A
Reserved
0
0