hi5728 Intersil Corporation, hi5728 Datasheet
hi5728
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hi5728 Summary of contents
Page 1
... Data Sheet 10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter The HI5728 is a 10-bit, dual 125MSPS D/A converter which is implemented in an advanced CMOS process designed for high speed applications where integration, bandwidth and accuracy are essential. Operating from a single +5V or +3V supply, the converter provides 20.48mA of full scale output current and includes an input data register ...
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... REFERENCE SELECT REFLO REFIO FSADJ SLEEP (LSB) QD0 QD1 QD2 QD3 QD4 LATCH QD5 QD6 QD7 QD8 QCLK AV AGND DV DGND HI5728 IOUTA 36 LATCH UPPER 31 5-BIT DECODER BIAS GENERATION 36 LATCH UPPER 31 5-BIT DECODER QOUTA QOUTB IOUTB CASCODE CURRENT SOURCE 5 LSBs 36 + SWITCH ...
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... Typical Applications Circuit 50Ω ID6 ID5 ID4 ID3 ID2 ID1 ID0 (LSB) SLEEP DV DD 0.1µ 0.1µ 0.1µF FERRITE +5V OR +3V SUPPLY BEAD + 10µH 10µF 0.1µF 3 HI5728 I /Q CLK CLK 0.1µF 0.1µ ...
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... DD 43 ICLK 42 QCLK 4 HI5728 PIN DESCRIPTION Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q channel. Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I channel. Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20µ ...
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... LSB, equivalent to 10 Bits) (Note 25Ω (Note 7) L Full Scale Step Full Scale Step IOUTFS = 20mA IOUTFS = 2mA o θ 150 for All Typical Values. Data given is A HI5728IN - MIN TYP MAX UNITS Bits ±0 LSB ± ...
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... Electrical Specifications AV DD per channel except for ‘Power Supply Characteristics.’ (Continued) PARAMETER AC CHARACTERISTICS (Per Channel) - HI5728IN - 125MHz Spurious Free Dynamic Range, SFDR Within a Window Total Harmonic Distortion (THD) to Nyquist Spurious Free Dynamic Range, SFDR to Nyquist AC CHARACTERISTICS (Per Channel) - HI5728/6IN - 60MHz ...
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... IOUTFS = 2mA) (Note 6) (3V, IOUTFS = 20mA) (Note 6) (3V, IOUTFS = 2mA) (Note 6) (5V, IOUTFS = 20mA) (Note 10) (3.3V, IOUTFS = 20mA) (Note 10) (3V, IOUTFS = 20mA) (Note 10) Single Supply (Note for All Typical Values. Data given is A HI5728IN - MIN TYP MAX UNITS 2 ...
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... OUTPUT FREQUENCY (MHz) FIGURE 3. SFDR CLOCK = 50MSPS OUT 6dBFS -12dBFS 60 55 0dBFS OUTPUT FREQUENCY (MHz) FIGURE 5. SFDR CLOCK = 125MSPS OUT 8 HI5728 76 74 -6dBFS 1.4 1.6 1 ...
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... OUT FIGURE 9. SFDR CLOCK = 100MSPS OUT -40 - TEMPERATURE ( FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS 9 HI5728 (Continued) 75 25MSPS 70 50MSPS 125MSPS - AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, f ...
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... FREQUENCY (MHz) FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS 0.4 0.2 0 -0.2 -0.4 0 200 400 600 CODE FIGURE 17. DIFFERENTIAL NONLINEARITY 10 HI5728 (Continued) -10 Fclk = 100MSPS f = 100MSPS CLK -20 Fout = 13.5/14.5MHz = 13.5/14.5MHZ COMBINED PEAK -30 MTPR = 62.9dBc SFDR = 62.9dBc -40 14dB EXTERNAL -50 -60 -70 -80 -90 50 -100 ...
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... CLOCK = 5MSPS OUT 80 75 -6dBFS 70 -12dBFS 65 60 0dBFS OUTPUT FREQUENCY (MHz) FIGURE 22. SFDR CLOCK = 50MSPS OUT 11 HI5728 (Continued) 320 310 300 290 280 270 260 250 240 230 220 210 CLOCK RATE (MSPS) CLK / 80 -6dBFS 75 ...
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... AMPLITUDE (dBFS) FIGURE 26. SFDR vs AMPLITUDE (MA) OUT FIGURE 28. SFDR CLOCK = 100MSPS OUT 12 HI5728 (Continued FIGURE 25. SFDR vs AMPLITUDE 25MSPS 70 65 50MSPS 60 100MSPS FIGURE 27 ...
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... ANALYZER ATTENUATION -70 -80 -90 -100 -110 0 5MHz/DIV. FREQUENCY (MHz) FIGURE 32. TWO-TONE, CLOCK = 100MSPS -20 -30 f -40 -50 -60 -70 -80 -90 -100 -110 0.5 1.95MHz/DIV. FREQUENCY (MHz) FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS 13 HI5728 (Continued) -10 -20 2.5MHz -30 10.1MHz -40 -50 -60 -70 -80 40.4MHz -90 -100 -110 100MSPS CLK f = 13.5/14.5MHz ...
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... Typical Performance Curves, 3V Power Supply 0.4 0.2 0 -0.2 -0.4 0 200 400 600 CODE FIGURE 36. DIFFERENTIAL NONLINEARITY FIGURE 38. POWER vs CLOCK RATE HI5728 (Continued) 0.4 0.2 0 -0.2 -0.4 800 1000 152 148 144 140 136 132 128 124 120 CLOCK RATE (MSPS) f CLK / OUT 0 200 400 600 CODE FIGURE 37 ...
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... Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured 15 HI5728 50% 1 LSB ERROR BAND FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT t t ...
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... The units are ppm per C. Detailed Description The HI5728 is a dual, 10-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 125MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. It consumes less than 330mW of power when using a +5V supply with the data switching at 100MSPS ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 HI5728 equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0 ...