hi3-7152k-5 Intersil Corporation, hi3-7152k-5 Datasheet - Page 12

• Manufacturer Part Number: hi3-7152k-5
• Description: 10-bit High Speed Converter With Track Hold
• Manufacturer: Intersil Corporation

As in any analog system, good supply bypassing is
necessary in order to achieve optimum system performance
(minimize conversion errors). The power supplies should be
bypassed with at least a 20µF tantalum and 0.1µF ceramic
capacitors to GND. The reference input should be bypassed
with a 0.1µF ceramic capacitor to AG. The capacitor leads
should be as short as possible.
The pins on the HI-7152 are arranged such that the analog
pins are well isolated from the digital pins. In spite of this
arrangement, there is always pin to pin coupling. Therefore
the analog inputs to the device should not be driven from
very high output impedance sources. PC board layout
should screen the analog and reference inputs with AG.
Using a soldier mask is good practice and helps reduce
leakage due to moisture contamination on the PC board.
Applications
Typical applications are illustrated in Figure 5 through 7 for
the slow memory, fast memory, and DMA modes of
operation. The output data is configured for 16-bit bus oper-
ation of these three applications. By tying BUS and DG and
connecting the HBE input to the system address decoder,
the output data can be configured for 8-bit bus systems.
+
2.5V
-
P.S.
FIGURE 4. GROUND AND POWER SUPPLY DECOUPLING
+
-
P.S.
-5V
ANALOG INPUT
0.1µF
0.1µF
V+
20µF
HI-7152
6-12
10
11
12
13
14
Figure 8 illustrates an application where the HI-7152 is used
with an analog multiplexer to form a multi-channel data
acquisition system. Either slow memory or fast memory
modes of operation can be selected. Fast memory mode
should be selected for maximum throughput. Multiplexer
channel acquisition should occur approximately 500ns after
HOLD goes high. This allows 2 clocks minus 0.5µs for the
input to settle. With a 600kHz clock the input has up to 2.8µs
to settle.
An intelligent system which performs a scale factor
adjustment under software control with the addition of a
programmable gain block between the multiplexer and
HI-7151 is illustrated in Figure 9. The microprocessor first
performs a conversion and then checks the over-range
status (OVR) bit. If the OVR bit is high, the microprocessor
addresses a precision gain circuit for scale factor adjustment
and initiates another conversion. The microprocessor must
keep track of the selected scale factor.
The accuracy of the programmable gain amplifier should be
better than 0.05%. For optimum system performance, op
amp frequency response, settling time, and charge injection
of the analog switch must be considered.
Figure 10 illustrates the HI-7152 interfaced to FIFO
memories for use in DMA applications.
1
2
3
4
5
6
7
8
9
GND
V-
V
AG
V
SET
BUSY
CLK
HOLD
WR
CS
RD
SMODE
DG
REF
IN
HI-7152
20µF
OVR
HBE
BUS
0.1µF
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
V+
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P.S.
5V
-
+