hi3-7153j-5 Intersil Corporation, hi3-7153j-5 Datasheet - Page 14

• Manufacturer Part Number: hi3-7153j-5
• Description: 8-channel, 10-bit High Speed Sampling Converter
• Manufacturer: Intersil Corporation

Analog Multiplexer
The multiplexer channel assignments are shown in Table 1
and can be randomly addressed. Address inputs A0 - A2 are
binary coded and are TTL/CMOS compatible. During power
up the circuit is initialized and multiplexer channel A
selected. The multiplexer address is transparent when ALE
is high and CS is low. The address data is latched on the
falling edge of the ALE signal. The multiplexer channel
acquisition timing (Timing Diagrams, Slow Memory Mode)
occurs approximately 500ns after the rising edge of HOLD.
The multiplexer features a typical break-before-make switch
action of 44ns.
Track And Hold
A Track and Hold amplifier has been fully integrated on the
front end of the A/D converter. Because of the sampling
nature of this A/D converter, the input is required to stay
constant only during the first clock cycle. Therefore, the
Track and Hold (T/H) amplifier ‘‘holds’’ the input voltage only
during the first clock cycle and it acquires the input voltage
for the next conversion during the remaining two clock
cycles. The high input impedance of the T/H input amplifier
simplifies analog interfacing. Input signals up to ±V
be directly connected to the A/D without buffering. The T/H
amplifier typically settles to within
output code table is presented in Table 2.
* The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.
LSB = 2(V
≥ +V
+V
+1LSB
0
-1LSB
-V
≤ -V
REF
REF
REF
REF
- 1LSB
- 1LSB
REF
ANALOG INPUT*
TRACK AND HOLD
)/1024
SCA AUTO-ZERO
AUTO-ZERO (AZ)
INTERNAL DATA
COMPARATOR
10 BITS + OVR
2.500 to V+ (+OVR)
2.49512 (+Full Scale)
0.00488
0.000
-0.00488
-2.500 (-Full Scale)
2.50488 to V- (-OVR)
CLOCK
(SCAZ)
V
REF
= 2.500V
N CONVERSION
1
SAMPLE V
/
SAMPLE
4
V
IN
LSB in 1.5µs. The A/D
HOLD V
1
(N)
FIGURE 2. INTERNAL ADC TIMING DIAGRAM
OVR
IN
TABLE 2. A/D OUTPUT CODE TABLE
1
0
0
0
0
0
1
IN
CONVERT
(N)
UPPER
5 BITS
(N)
2
MSB
9
0
0
0
0
1
1
1
REF
IN0
HI-7153
can
is
8
0
1
0
0
1
0
0
3
14
SAMPLE RESIDUAL
AMPLIFY RESIDUAL
The timing signals for the Track and Hold amplifier are
generated internally, and are also provided externally
(HOLD) for synchronization purposes.
All of the internal amplifiers are offset trimmed during
manufacturing to give improved accuracy and to minimize
the number of external components. If necessary, offset
error can be adjusted by using digital post correction.
OUTPUT DATA (2’S COMPLEMENT)
A2
7
0
1
0
0
1
0
0
TRACK V
0
0
0
0
1
1
1
1
4
ADDRESS AND CONTROL INPUTS
TABLE 1. MULTIPLEXER CHANNEL SELECTION
6
0
1
0
0
1
0
0
IN
A1
0
0
1
1
0
0
1
1
(N+1)
5
5
0
1
0
0
1
0
0
A0
0
1
0
1
0
1
0
1
CONVERT
LOWER
5 BITS
4
0
1
0
0
1
0
0
6
SAMPLE V
N+1 CONVERSION
CS
0
0
0
0
0
0
0
0
3
0
1
0
0
1
0
0
V
HOLD V
SAMPLE
V
IN
IN
IN
(N+1)
(N) DATA
(N+1)
ALE
1
1
1
1
1
1
1
1
IN
2
0
1
0
0
1
0
0
(N+1)
SELECTED
CHANNEL
ANALOG
1
0
1
0
0
1
0
0
A
A
A
A
A
A
A
A
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
LSB 0
0
1
1
0
1
0
0