hi7190 Intersil Corporation, hi7190 Datasheet
hi7190
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hi7190 Summary of contents
Page 1
... The HI7190 and HI7191 are functionally the same device, but the HI7190 has tighter linearity specifications. The HI7190 contains a serial I/O port and is compatible with most synchronous transfer formats including both the Motorola 6805/11 series SPI and Intel 8051 series SSR protocols ...
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... HI7190IPZ - HI7190IB HI7190IB - HI7190IBZ HI7190IBZ - (Note) HI7190IBZ-T HI7190IBZ - (Note) HI7190EVAL Evaluation Kit *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets ...
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... Typical Application Schematic +5V INPUT + - INPUT REFERENCE -5V 0.1μF 3 HI7190 10MHz 17 16 OSC OSC 4.7μF 0.1μ INHI 11 V INLO +2.5V V RHI 8 V RLO 4.7μF + AGND + 4.7μF 0.1μF 1 SCLK 3 SDIO DATA I/O 2 DATA OUT SDO 19 SYNC ...
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... DIGITAL INPUTS Input Logic High Voltage Input Logic Low Voltage Input Logic Current HI7190 Thermal Information Thermal Resistance (Typical, Note 1) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150° Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C ...
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... LSB = 298nV at 24 bits for a Full Scale Range of 5V REF RHI RLO. 10. These errors are on the order of the output noise shown in Table 1. 11. All inputs except OSC . The OSC input HI7190 = +5V -5V +5V +2.5V RHI = 10MHz, Bipolar Input Range Selected TEST CONDITIONS -100μ ...
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... ACC DRDY CS SCLK SDIO 1 6 HI7190 t SCLK t DSU t t SCLKPW SCLKPW t DHLD 1ST BIT FIGURE 1. DATA WRITE TO HI7190 1ST BIT t DV FIGURE 2. DATA READ FROM HI7190 5 6 FIGURE 3. DATA READ FROM HI7190 2ND BIT 2ND BIT t DRDY 7 8 FN3612.10 June 27, 2006 ...
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... Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial Interface using a 2-wire serial protocol Chip Select Input. Used to select the HI7190 for a serial data transfer cycle. This line can be tied to DGND. 5 DRDY An Active Low Interrupt indicating that a new data word is available for reading. ...
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... GAIN = 8 10 124.7 20.4 25 120.6 19.7 30 119.2 19.5 50 117.5 19.2 60 116.8 19.1 100 112.1 18.3 250 101.4 16.5 500 95.3 15.5 1000 83.1 13.5 2838.6 2000 68.3 11.1 15494.7 8 HI7190 RMS NOISE HERTZ (μV) (μV) GAIN = 16 10 9.8 1.5 25 13.6 2.1 30 16.6 2.5 50 19.5 3.0 60 21.2 3.2 100 30.7 4.6 250 166.7 25.3 500 505.3 76.6 1000 318.5 2000 2221.4 GAIN = 32 10 14.0 2.1 25 20.9 3 ...
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... The input signal is continuously sampled at the input to the HI7190 at a clock rate set by the oscillator frequency and the selected gain. This signal then passes through the sigma delta modulator (which includes the PGIA) and emerges as a pulse train whose code density contains the analog signal information ...
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... When the HI7190 is powered up it needs to be reset by pulling the RESET line low. The reset sets the internal registers of the HI7190 as shown in Table 2 and puts the part in the bipolar mode with a gain of 1 and offset binary coding. The filter notch of the digital filter is set at 30Hz while the I/O ...
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... IN The Programmable Gain Instrumentation Amplifier allows the user to directly interface low level sensors and bridges directly COMPARATOR to the HI7190. The PGIA has 4 selectable gain options which are implemented by multiple sampling of the input + - signal. Input signals can be gained up further to 16, 32 128 ...
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... See Figure 7 for an applications circuit. RATIOMETRIC CONFIGURATION LOAD CELL FIGURE 7. BURN-OUT CURRENT SOURCE CIRCUIT Digital Section Description A block diagram of the digital section of the HI7190 is shown in Figure 8. This section includes a low pass decimation filter, conversion controller, calibration logic, serial interface, and clock generator. MODULATOR CLOCK ...
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... The result of the input not settling to the proper value is a system gain error which can be eliminated by system calibration of the HI7190. Clocking/Oscillators The master clock into the HI7190 can be supplied by either a crystal connected between the OSC shown in Figure 10A or a CMOS compatible clock signal connected to the OSC ...
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... Calibration Register. The user must apply the +Full Scale . From INLO voltage to the HI7190 analog inputs and allow the signal to settle before selecting this mode. After 4 conversion periods the DRDY line will activate signaling the calibration is complete and valid data is present in the Data Output Register ...
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... Reserved This mode is not used in the HI7190 and should not be selected. There is no internal detection logic to keep this condition from being selected and care should be taken not to assert this bit combination. ...
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... MCS51 and MCS96 family of microcontrollers, or other similar processors. SCLK - Serial clock. The serial clock pin is used to synchronize data to and from the HI7190 and to run the port state machines. In Synchronous External Clock Mode, SCLK is configured as an input, is supplied by the user, and can run 5MHz rate ...
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... Programming the Serial Interface It is useful to think of the HI7190 interface in terms of communication cycles. Each communication cycle happens in 2 phases. The first phase of every communication cycle is the writing of an instruction byte. The second phase is the data transfer as described by the instruction byte ...
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... Negative Full Scale Calibration Register. Write operations are done using the SDIO, CS and SCLK lines only, as all data is written into the HI7190 via the SDIO line even when using the 3-wire configuration. Figures 14 and 15 show typical write timing diagrams. ...
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... To assert a read cycle, during the instruction phase of the communication cycle, the Instruction Byte should be set to a read transfer (R/W = 0). When reading the serial port, data is driven out of the HI7190 on the falling edge of SCLK. Data can be registered externally on the next rising edge of SCLK. ...
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... These bits determine the filter cutoff frequency, the position of the first notch and the data rate the HI7190. The first notch of the filter is equal to the MD1 MD0 B/U decimation rate and can be determined by the formula: f ...
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... MSB or LSB first. This bit allows the user to change the order that data can be transmitted or received by the HI7190. When this bit is cleared (MSB = 0) the MSB is the first bit in a serial data transfer. If set (MSB = 1), the LSB is the first bit transferred in the serial data stream. This bit is cleared after a RESET is applied to the part ...
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... However single data byte is written to byte assumed that the gain has NOT been changed the user to re-calibrate the HI7190 after the gain has been changed by this method recommended that the entire Control Register be written to when changing the selected gain ...
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... DIE DIMENSIONS 3550μm x 6340μm METALLIZATION Type: AlSiCu Å Thickness:Metal 2, 16k Å Metal 1, 6k Metallization Mask Layout CS DRDY DGND HI7190 SUBSTRATE POTENTIAL (POWERED UP PASSIVATION Type: Sandwich Å Thickness:Nitride 8k Å USG 1k HI7190 OSC OSC DV AGND FN3612.10 June 27, 2006 ...
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... B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 24 HI7190 E20.3 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE SYMBOL E A2 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 HI7190 M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...