hi7131 Intersil Corporation, hi7131 Datasheet - Page 9

• Manufacturer Part Number: hi7131
• Description: 3 1/2 Digit, Low Power, High Cmrr, Lcd/led Display-type A/d Converters
• Manufacturer: Intersil Corporation

Figure 3 shows a typical waveform of the integrator output
for 2 different positive input values and the associated repre-
sentation of the counter output for those inputs. T
time period of integrating phase. t
measurement for 2 different inputs.
The dual slope integrating technique puts the primary
responsibility for accuracy on the reference voltage. The val-
ues of R
important, provided they are stable during each conversion
cycle. This can be expressed mathematically as follows:
It can be seen that the output reading of the ADC is only
proportional to the ratio of V
also demonstrates that for the maximum display reading
(i.e., 1999) we will have V
V
T
t
Accumulated Counts
TIMING SIGNALS
DEINT
V
V
INT
IN
INT
INT
: Input Average Value During Integration Time
REFERENCE
V
VOLTAGE
IN
=
3
MAXIMUM COUNT: 1999
=
=
1
INT
=
1000
/
2
--------------------------- -
R
--------------------------- -
R
A ccumulated Counts
+V
-V
V
DIGIT BCD COUNTER
INT
INT
and C
IN
REF
REF
------------
f
1
T
CLK
C
C
DISPLAY DRIVERS
INT
1
INT
INT
INT
LATCHES
DISPLAY
T INT
=
=
AND
0
and the clock frequency (f
V
---------------------------------- -
1000
SWITCH
DRIVE
R
V
REF
INT
IN
IN
-------------- -
V
dt
t
V
IN
DEINT
C
= 1.999 V
REF
IN
R
INT
------------
f
=
LATCH
CLK
over V
INT
1
ENABLE
--------------------------- -
R
FIGURE 91. DUAL SLOPE INTEGRATING A/D CONVERTER
=
RESET
INT
1
Display Reading
CLK
1
C
and t
REF
REF
INT
INTEGRATOR
. The last equation
T DEINT
. This implies that
C
2
f
+
-
CLK
INT
are the end of
0
CLK
V
INT
REF
HI7131, HI7133
) are not
GENERATOR
CONTROL
is the
dt
COMPARATOR
CLOCK
LOGIC
3-1834
+
-
in this configuration the full scale range of the converter is
twice its reference voltage.
The inherent advantages of integrating A/D converters are;
very small nonlinearity error, no possibility of missing codes
and good high frequency noise rejection.
Furthermore, the integrating converter has extremely high
normal mode rejection of frequencies whose periods are an
integral multiple of the integrating period (T
can be used to reject the line frequency related noises which
are riding on input voltage by appropriate selection of clock
frequency. This is shown in Figure 4.
FIGURE 92. NOISE REJECTION FOR INTEGRATING TYPE A/D
30
20
10
0.1/T
0
INT
1000
0
CONVERTER
VARIABLE
SLOPE
INTEGRATION
INTEGRATOR
OUTPUT
FOR POSITIVE
INPUT
COUNTER
OUTPUT
FIXED
TIME
T
INT
T
f = INPUT OR NOISE FREQUENCY
1/T
INT
FIXED
SLOPE
INT
DEINTEGRATION
= INTEGRATION PERIOD
VARIABLE
TIME
t
1
INT
). This feature
t
2
10/T
t
t
INT
f