clc5632 National Semiconductor Corporation, clc5632 Datasheet - Page 14

• Manufacturer Part Number: clc5632
• Description: Dual, High Output, Programmable Gain Buffer
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Division
Load Termination
The CLC5632 can source and sink near equal amounts of
current. For optimum performance, the load should be tied to
V
Driving Cables and Capacitive Loads
When driving cables, double termination is used to prevent
reflections. For capacitive load applications, a small series
resistor at the output of the CLC5632 will improve stability
and settling performance. The Frequency Response vs. C
plot, shown below in Figure 10 , gives the recommended
series resistance value for optimum flatness at various ca-
pacitive loads.
Transmission Line Matching
One method for matching the characteristic impedance (Z
of a transmission line or cable is to place the appropriate
resistor at the input or output of the amplifier. Figure 11
shows typical inverting and non-inverting circuit configura-
tions for matching transmission lines.
Non-Inverting gain applications:
Inverting gain applications:
The input and output matching resistors attenuate the signal
by a factor of 2, therefore additional gain is needed. Use C6
to match the output transmission line over a greater fre-
quency range. C6 compensates for the increase of the am-
plifier’s output impedance with frequency.
• Connect pin 2 as indicated in the table in the Closed
• Make R
•
• Connect R
• Make the resistors R
• Make R
CM
Loop Gain Selection section.
caused by the transmission line, or by parasitics.
.
Use R
FIGURE 10. Frequency Response vs. C
1
3
5
, R
\ R
to isolate the amplifier from reactive loading
3
2
directly to ground.
g
, R
= Z
6
, and R
O
.
4
, R
7
6
, and R
equal to Z
(Continued)
7
equal to Z
O
.
DS015003-48
O
.
L
O
L
)
14
Power Dissipation
Follow these steps to determine the power consumption of
the CLC5632:
1. Calculate the quiescent (no-load) power: P
(V
2. Calculate the RMS power at the output stage: P
−V
current across the external load.
3. Calculate the total RMS power: P
mum power that the DIP and SOIC, packages can dissipate
at a given temperature is illustrated in Figure 12 . The power
derating curve for any CLC5632 package can be derived by
utilizing the following equation:
where
T
given package (˚C/W)
Layout Considerations
A proper printed circuit layout is essential for achieving high
frequency performance. National provides evaluation boards
for the CLC5632 (CLC730038-DIP, CLC730036-SOIC) and
suggests their use as a guide for high frequency layout and
as an aid for device testing and characterization.
General layout and supply bypassing play major roles in high
frequency performance. Follow the steps below as a basis
for high frequency layout:
• Include 6.8µF tantalum and 0.1µF ceramic capacitors on
• Place the 6.8µF capacitors within 0.75 inches of the
• Place the 0.1µF capacitors less than 0.1 inches from the
V
V
JA
amb
1
2
CC
load
both supplies.
power pins.
power pins.
+
+
-
-
= Thermal resistance, from junction to ambient, for a
−V
= Ambient temperature (˚C)
) (I
R
R
EE
4
1
FIGURE 11. Transmission Line Matching
load
)
FIGURE 12. Power Derating Curve
), where V
Z
Z
0
0
R
R
5
R
2
3
load
and I
3
1
2
4
1k
CLC5632
load
1k
+
1k
-
+
-
are the RMS voltage and
1k
t
= P
DS015003-51
8
7
6
5
amp
Note: Channel 2 not shown.
C
R
+P
6
6
O
amp
The maxi-
O
Z
0
= (V
DS015003-49
= I
CC
CC
R
7
V
o