cs5165 ON Semiconductor, cs5165 Datasheet
cs5165
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cs5165 Summary of contents
Page 1
... With this method, the MOSFETs do not overheat or self destruct. The CS5165 is designed for use in both single processor desktop and multiprocessor workstation and server applications. The CS5165’s current sharing capability allows the designer to build multiple parallel and redundant power solutions for multiprocessor systems ...
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... GATE(H) C OFF GATE(L) 330 pF 0.1 μF V ID4 PGND V ID3 LGND V ID2 CS5165 V ID1 PWRGD V ID0 ENABLE Figure 1. Application Diagram 14.2 A for 300 MHz Pentium II ABSOLUTE MAXIMUM RATINGS* Operating Junction Temperature Lead Temperature Soldering: Storage Temperature Range ESD Susceptibility (Human Body Model second maximum above 183° ...
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ABSOLUTE MAXIMUM RATINGS Pin Name Pin Symbol IC Power Input Soft Start Capacitor Compensation Capacitor COMP Voltage Feedback Input Off−Time Capacitor Voltage ID DAC Inputs V ID0 High−Side FET Driver GATE(H) Low−Side FET Driver GATE(L) Enable Input ENABLE Power Good ...
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ELECTRICAL CHARACTERISTICS (continued ID4 ID2 ID1 ID0 ID3 ; Characteristic Fault Protection SS Charge Time Pulse Period Duty Cycle (Charge Time/Period) ...
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ELECTRICAL CHARACTERISTICS (continued ID4 ID2 ID1 ID0 ID3 ; Characteristic Voltage Identification DAC Accuracy (all codes except 11111) Measure V 25°C ≤ ...
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ELECTRICAL CHARACTERISTICS (continued ID4 ID2 ID1 ID0 ID3 ; Threshold Accuracy DAC CODE % of Nominal DAC Output ID4 ID3 ID2 ID1 ...
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... Off−Time Capacitor Pin. A capacitor from this pin to LGND sets both the normal and extended off time. Output Enable Input. This pin is internally pulled logic Low (< 0.8) on this pin disables operation and places the CS5165 into a low current sleep mode. Input Power Supply Pin. High Side Switch FET driver pin. ...
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V CC 7.0 μ ENABLE − Circuit Bias + 1.25 V Enable Comparator SS COMP Error Amplifier V ID0 + V ID1 5 BIT V − DAC ID2 V ID3 V ID4 −8.5% +8.5% + − − + ...
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TYPICAL PERFORMANCE CHARACTERISTICS 200 180 160 140 120 100 2000 4000 6000 8000 10000 12000 14000 16000 Load Capacitance (pF) Figure 3. GATE(L) Risetime vs. Load Capacitance 200 180 160 140 120 100 80 ...
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... 100 mV steps, the second steps, depending on the digital input code. If all five bits are left open, the CS5165 enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the V pin traditional controllers. The CS5165 is specifically designed to meet or exceed Intel’ ...
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... Soft Start COMP clamp and the voltage on the Soft Start pin. Power Supply Sequencing The CS5165 offers inherent protection from undefined start up conditions, regardless of the 12 V and 5.0 V supply power up sequencing. The turn on slew rates of the 12 V and 5.0 V power supplies can be varied over wide ranges without affecting the output voltage or causing detrimental effects to the buck regulator ...
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... Ripple LOAD Transient Response 2 The CS5165 V control loop’s 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be ...
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Conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre−positioned −40 mV (see Figures 15, 16, and 17). For best Transient ...
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M 25.0 ms Trace 4− 5.0 V Supply Voltage (2.0 V/div.) Trace 3− Soft Start Timing Capacitor (1.0 V/div.) Trace 2− Inductor Switching Node (2.0 V/div.) Figure 18. Demonstration Board Hiccup Mode Short Circuit Protection. Gate Pulses are Delivered While ...
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... Figure 24 shows the relationship between the regulated output voltage V Power Good from interrupting the CPU unnecessarily, the CS5165 has a built−in delay to prevent noise at the V from toggling Power Good. The internal time delay is designed to take about 75 μs for Power Good to go low and 65 μ ...
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... Regulation Conditions that are Present for a Duration Less Than the Built In Delay Selecting External Components The CS5165 buck regulator can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection ...
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... DC accuracy spec, the voltage drop developed across the resistor must be calculated as follows: V DROOP(TYP) + With the CS5165 DAC accuracy being 1.0%, the internal error amplifier’s reference voltage is trimmed so that the output voltage will high at no load. With no load, there drop across the resistor, producing an output voltage tracking the error amplifier output voltage, including the offset ...
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The total voltage drop due to a load step is ΔV−40 mV and the deviation from the nominal output voltage smaller than it would be if there was no droop ...
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... Layout Guidelines When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the CS5165. 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors 14 6.1 ms are major concerns for a good layout ...
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... V MBRS120 MBRS120 MBRS120 1.0 μ ID0 V V CS5165 ID1 V ID2 V ID3 V ID4 C OFF 330 pF SS COMP 0.1 μF 0.1 μF Figure 28. Additional Application Diagram 14.2 A for 300 MHz Pentium II 1200 μF/10 V × 3 1.0 μF Si4410DY GATE(H) 1.2 μH Si9410DY V GATE(L) PGND ENABLE PWRGD 3 ...
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... PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0. Unit °C/W °C/W ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CS5165/D ...