lm8322 National Semiconductor Corporation, lm8322 Datasheet - Page 10

• Manufacturer Part Number: lm8322
• Description: Mobile I/o Companion Supporting Key-scan, I/o Expansion, Pwm, And Access.bus Host Interface
• Manufacturer: National Semiconductor Corporation

www.national.com
10.0 Reset
The LM8322 may be reset by either an external reset, RE-
SET command, or an internally generated power-on reset
(POR) signal. The RESET input must not be allowed to float.
If the external RESET input is not used, it must be connected
to VCC, either directly or through a pull-up resistor.
10.1 EXTERNAL RESET
The device enters a reset state immediately when the RE-
SET input is driven low. RESET must be held low for a
minimum of 700 ns to guarantee a valid reset. If RESET is
asserted at power-on, it must be held low until V
the minimum operating voltage (1.62V). If an RC circuit is
used to drive RESET, it must have a time constant 5 times
(5×) greater than the V
When RESET goes low, the I/O ports are initialized immedi-
ately, any observed delay being only propagation delay.
XTAL_OUT
CONFIG_1
CONFIG_2
ACB_SDA
ACB_SCL
XTAL_IN
KP-X00
KP-X01
KP-X02
KP-X03
KP-X04
KP-X05
KP-X06
KP-X07
KP-Y00
KP-Y01
KP-Y02
KP-Y03
KP-Y04
KP-Y05
KP-Y06
KP-Y07
KP-Y08
KP-Y09
KP-Y10
KP-Y11
PWM_0
PWM_1
PWM_2
RESET
Pins
IRQ
CC
rise time to this level.
High-impedance mode.
High-impedance mode.
High-impedance mode.
High-impedance mode.
High-impedance mode.
High-impedance mode.
High-impedance mode.
Open-drain mode.
High-impedance mode.
Weak pullup device.
High-impedance mode.
After Reset
TABLE 3. Pin Configuration After Reset
CC
rises above
Input mode with an on-chip pullup enabled.
High-impedance mode, until host configures them as keypad inputs
or GPIO.
Active drive low.
High-impedance mode, until host configures them as keypad outputs
or GPIO.
The ACCESS.bus slave address must be selected with external
pullup or pulldown resistors or direct connections to V
Active drive low.
High-impedance mode.
Open-drain mode.
High-impedance mode. Terminate to V
Weak pullup device.
High-impedance mode.
10
When the RESET pin goes high, the LM8322 comes out of
the reset state within about 1400 ns.
10.2 POWER-ON RESET (POR)
The POR circuit is always enabled. When V
POR threshold voltage VPOR (about 1.2–1.5V), an on-chip
reset signal is asserted. The V
than 20 µs and less than 10 ms, otherwise the on-chip reset
signal may deassert before V
ating voltage. While V
in reset and a timer clocked by the on-chip RC clock is preset
with 0xFF (256 clock cycles). When V
greater than VPOR, the timer starts counting down. When it
underflows, the on-chip reset signal is deasserted and the
LM8322 begins operation.
10.3 PIN CONFIGURATION AFTER RESET
Table 2 shows the pin configuration after reset.
After LM8322 Initialization
CC
is below VPOR, the LM8322 is held
CC
CC
or GND if not used.
CC
reaches the minimum oper-
rise time must be greater
CC
CC
CC
reaches a value
rises above the
or GND.