lm8322 National Semiconductor Corporation, lm8322 Datasheet - Page 39

• Manufacturer Part Number: lm8322
• Description: Mobile I/o Companion Supporting Key-scan, I/o Expansion, Pwm, And Access.bus Host Interface
• Manufacturer: National Semiconductor Corporation

System Clock (mclk) (Note 8)
Processing and Command Execution Cycle (t
(Note 8)
System Clock, Processing and Command
Execution Cycle Variation(Note 8)
General-Purpose I/O (GPIO)
Output Rise Time(Note 8)
Output Fall Time(Note 8)
Condition (tBUFi) (Note 8)
ACCESS.bus Output Signals (Note 9)
Condition (tBUFo)(Note 9)
20.0 AC Electrical Characteristics
(Temperature: -40°C
Data sheet specification limits are guaranteed by design, test, or statistical analysis.
Bus Free Time Between Stop and Start
SCL Setup Time (tCSTOsi) (Note 8)
SCL Hold Time (tCSTRhi) (Note 8)
SCL Setup Time (tCSTRsi) (Note 8)
Data High Setup Time (tDHCsi) (Note 8)
Data Low Setup Time (tDLCsi) (Note 8)
SCL Low Time (tSCLlowi) (Note 8)
SCL High Time (tSCLhighi) (Note 8)
SDA Hold Time (tSDAhi) (Note 8)
SDA Setup Time (tSDAsi) (Note 8)
Bus Free Time Between Stop and Start
SCL Setup Time (tCSTOso) (Note 8)
SCL Hold Time (tCSTRho) (Note 8)
SCL Setup Time (tCSTRso) (Note 8)
Data High Setup Time (tDHCso) (Note 8)
Data Low Setup Time (tDLCso) (Note 8)
SCL Low Time (tSCLlowo) (Note 8)
SCL High Time (tSCLhigho) (Note 8)
SDA Hold Time (tSDAho) (Note 8)
SDA Valid Time (tSDAso) (Note 8)
Note 8: Guaranteed by design, not tested.
Note 9: The ACCESS.bus interface implements and meets the timing necessary for interface to the I
designed with open-drain output for bidirectional operation. The will not meet the AC timing and current/voltage requirements of the full bus specification.
ACCESS.bus Input Signals(Note 9)
Parameter
≤
T
A
≤
+85°C)
C
)
Internal RC
1.62V
1.62V
C
Before Stop Condition k
After Start Condition
Before Start Condition
Before SCL Rising Edge (RE)
Before SCL RE
After SCL Falling Edge (FE)
After SCL RE
After SCL FE
Before SCL RE
Before Stop Condition
After Start Condition
Before Start Condition
Before SCL RE
Before SCL RE
After SCL FE
After SCL RE
After SCL FE
Before SCL RE
LOAD
≤
≤
= 50 pF
V
V
CC
CC
≤
≤
39
Conditions
1.98V
1.98V
2
C and SMBus protocol at logic levels. The bus drivers are
t
t
t
t
t
t
t
SCLhigho
SCLhigho
SCLhigho
SCLhigho
SCLhigho
SCLhigho
SCLhigho
Min
12
12
16
16
8
8
8
2
2
0
2
7
7
Typ
0.5
21
Max
www.national.com
15
15
7
Units
MHz
mclk
mclk
mclk
mclk
mclk
mclk
mclk
mclk
mclk
mclk
mclk
mclk
mclk
μs
ns
ns
%