adv7181d Analog Devices, Inc., adv7181d Datasheet - Page 10

• Manufacturer Part Number: adv7181d
• Description: 10-bit, 10-channel, Multiformat Sdtv/hdtv Video Decoder And Rgb Graphics Digitizer
• Manufacturer: Analog Devices, Inc.

ADV7181D
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3, 10, 24, 57
4, 11
28 to 25, 19 to 12,
8 to 5, 62 to 59
9
20
21
22
23, 58
29
30
31
32
Mnemonic
INT
HS/CS
GND
DVDDIO
P0 to P19
SFL/SYNC_OUT
LLC
XTAL1
XTAL
DVDD
PWRDWN
ELPF
PVDD
FB
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
SFL/SYNC_OUT
DVDDIO
DVDDIO
Output
Output
Ground
Power
Output
Output
Output
Output
Input
Power
Input
Output
Power
Input
Type
HS/CS
GND
GND
P15
P14
P13
P12
P11
P10
INT
P9
P8
P7
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Description
Interrupt. This pin can be active low or active high. When SDP/CP status bits change,
this pin is triggered. The set of events that triggers an interrupt is under user control.
Horizontal Synchronization Output Signal (HS). Available in SDP and CP modes.
Digital Composite Synchronization Signal (CS). Available in CP mode only.
Ground.
Digital I/O Supply Voltage (3.3 V).
Video Pixel Output Port. See Table 10 and Table 11 for output configuration modes.
Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be
used to lock the subcarrier frequency when this decoder is connected to any Analog
Devices digital video encoder.
Sliced Synchronization Output Signal (SYNC_OUT). Available in CP mode only.
Line-Locked Clock Output for Pixel Data. The range is 12.825 MHz to 75 MHz.
This pin should be connected to the 28.63636 MHz crystal or left unconnected if an
external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7181D.
In crystal mode, the crystal must be a fundamental crystal.
Input Pin for the 28.63636 MHz Crystal. This input can be overdriven by an external
3.3 V, 28.63636 MHz clock oscillator source to clock the ADV7181D.
Digital Core Supply Voltage (1.8 V).
Power-Down Input. A Logic 0 on this pin places the
External Loop Filter Output. The recommended external loop filter must be connected
to this pin (see the Recommended External Loop Filter Components section).
PLL Supply Voltage (1.8 V).
Fast Blank Input. Fast switch between CVBS and RGB analog signals.
PIN 1
Figure 6. Pin Configuration
Rev. 0 | Page 10 of 24
ADV7181D
(Not to Scale)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A
A
A
A
CAPC2
CML
REFOUT
AVDD
CAPY2
CAPY1
A
A
A
A
A
SOG
IN
IN
IN
IN
IN
IN
IN
IN
IN
9
8
7
6
5
4
3
2
1
ADV7181D
in power-down mode.
Data Sheet