adv7197 Analog Devices, Inc., adv7197 Datasheet
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adv7197
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adv7197 Summary of contents
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... YCrCb. This data is accepted in HDTV format at 74.25 MHz or 74.1758 MHz. For any other high definition standard but SMPTE274M or SMPTE296M, the Async Timing Mode can be used to input data to the ADV7197. For all standards, ADV is a registered trademark of Analog Devices, Inc. Multiformat HDTV Encoder with ...
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... ADV7197–SPECIFICATIONS ( SPECIFICATIONS 70 C] unless otherwise noted.) Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity DIGITAL OUTPUTS Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS Input High Voltage, V ...
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... REF ADV7197 , R = 300 . All specifications LOAD MIN Unit Test Conditions Bits LSB LSB 400 µA SOURCE 3.2 mA SINK µ 0 µ 0 2 DAC A mA DAC ...
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... ADV7197–SPECIFICATIONS 5 V DYNAMIC–SPECIFICATIONS Parameter Luma Bandwidth Chroma Bandwidth Signal-to-Noise Ratio Chroma/Luma Delay Inequality Specifications subject to change without notice. 3.3 V DYNAMIC–SPECIFICATIONS Parameter Luma Bandwidth Chroma Bandwidth Signal-to-Noise Ratio Chroma/Luma Delay Inequality Specifications subject to change without notice TIMING–SPECIFICATIONS ...
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... Clock Cycles ... ... Cr0 Cb1 Cr1 ... ADV7197 = 2470 , R = 300 . All specifications SET LOAD Conditions After This Period the 1st Clock Is Generated Relevant for Repeated Start Condition HDTV Mode Async Timing Mode For 4:4:4 Pixel Input Format Yxxx Yxxx Cbxxx ...
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... ADV7197 CLOCK PIXEL INPUT DATA t 11 CLOCK PIXEL INPUT DATA ... ... Cb0 Cb1 Cb2 Cb3 ... Cr0 Cr1 Cr2 Cr3 ... ... ... ... ... t 12 Yxxx Yxxx Cbxxx Cbxxx Crxxx Crxxx t 9 – CLOCK HIGH TIME t 10 – ...
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... CLK CYCLES FOR 1080i MIN CLK CYCLES FOR 720P MIN B = 236 CLK CYCLES FOR 1080i MIN B = 300 CLK CYCLES FOR 720P MIN t 3 SDA SCL ADV7197 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7197 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). This input resets the on-chip timing generator and sets the ADV7197 into Default Register setting. Reset is an active low signal. TTL Address Input. This signal sets up the LSB of the MPU address. When this ...
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... Logic Level “0” corresponds to a write SWP 17.0SEC operation set by setting the ALSB pin of the ADV7197 to Logic Level “0” or Logic Level “1.” When ALSB is set to “0,” there is greater input bandwidth on the I high-speed data transfers on this bus. When ALSB is set to “ ...
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... SDA line is not pulled low on the ninth pulse Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7197 and the part will return to the idle condition. WRITE S ...
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... Mode Register 0. MR0 BIT DESCRIPTION Output Standard Selection (MR00–MR01) These bits are used to select the output levels from the ADV7197. If EIA 770.3 (MR01–00 = “00”) is selected, the output levels will be for blanking level, 700 mV for peak white (Y channel), ± ...
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... Figure 15 shows the various operations under the control of Mode Register 1. MR1 BIT DESCRIPTION Pixel Data Enable (MR10) When this bit is set to “0,” the pixel data input to the ADV7197 is blanked such that a black screen is output from the DACs. MR17 MR17–MR15 ...
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... ADV7197 MODE REGISTER 2 MR1 (MR27–MR20) (Address (SR4–SR0) = 02H) Figure 17 shows the various operations under the control of Mode Register 2. MR2 BIT DESCRIPTION Y Delay (MR20–MR22) With these bits it is possible to delay the Y signal with respect to the falling edge of the horizontal sync signal four pixel clock cycles. Figure 16 demonstrates this facility. Color Delay (MR23– ...
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... MR5 BIT DESCRIPTION Reserved (MR50) This bit is reserved for the revision code. RGB Mode (MR51) When RGB mode is enabled (MR51 = “1”) the ADV7197 accepts unsigned binary RGB data at its input port. This control is also available in Async Timing Mode. Sync on PrPb (MR52) By default the color component output signals Pr not contain any horizontal sync pulses ...
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... ADV7197 imperative that great care be given to the PC board layout. The layout should be optimized for lowest noise on the ADV7197 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length ...
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... OR 74.1758MHz CLOCK Due to the high clock rates used, long clock lines to the ADV7197 should be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane. ...
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... An optional analog reconstruction LPF might be required as an antialias filter if the ADV7197 is connected to a device that requires this filtering. The Eval ADV7196/ADV7197EB evaluation board uses the ML6426 Microlinear IC, which provides buffering and low-pass filtering for HDTV applications ...
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... DIGITAL HORIZONTAL BLANKING 272T 4T ANCILLARY DATA (OPTIONAL) OR BLANKING CODE 2199 2116 2156 0 44 ADV7197 Y-OUTPUT LEVELS FOR FULL I/P SELECTIONS OUTPUT VOLTAGE 700mV ACTIVE VIDEO 0mV –300mV PrPb-OUTPUT LEVELS FOR FULL I/P SELECTIONS OUTPUT VOLTAGE 700mV ACTIVE VIDEO 0mV –300mV Register Setting ...
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... ADV7197 747 748 749 750 FIELD 1 1124 1125 FIELD 2 561 562 VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 52-Lead Plastic Quad Flatpack (MQFP) (S-52) 0 ...