ADV7170SU AD [Analog Devices], ADV7170SU Datasheet
ADV7170SU
Related parts for ADV7170SU
ADV7170SU Summary of contents
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FEATURES ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder High Quality 10-Bit Video DACs SSAF (Super Sub-Alias Filter) Advanced Power Management Features CGMS (Copy Generation Management System) WSS (Wide Screen Signalling) Simultaneous Output Format NTSC-M, PAL-M/N, ...
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ADV7170/ADV7171–SPECIFICATIONS 5 V SPECIFICATIONS ( Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance, ...
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V SPECIFICATIONS (V AA Parameter 3 STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity 3 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL 3, 4 Input Current Input Capacitance, ...
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ADV7170/ADV7171–SPECIFICATIONS 5 V DYNAMIC SPECIFICATIONS Parameter 3, 4 Differential Gain 3, 4 Differential Phase 3, 4 Differential Gain 3, 4 Differential Phase 3, 4 SNR (Pedestal SNR (Pedestal SNR (Ramp SNR (Ramp ...
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V TIMING SPECIFICATIONS Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK ...
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ADV7170/ADV7171–SPECIFICATIONS 3.3 V TIMING SPECIFICATIONS Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, ...
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SDATA SCLOCK CLOCK HSYNC, CONTROL FIELD/VSYNC, I/PS BLANK PIXEL INPUT DATA HSYNC, CONTROL FIELD/VSYNC, O/PS BLANK TXTREQ t 16 CLOCK TXT 4 CLOCK CYCLES REV ...
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... PCB is 35.5 C/W. The junction-to-case thermal resis- tance ( ) is 13.75 C/W. JC Model ADV7170KS ADV7170SU ADV7171KS ADV7171SU CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7170/ADV7171 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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Input/ Mnemonic Output P15–P0 I CLOCK I HSYNC I/O FIELD/VSYNC I/O BLANK I/O SCRESET/RTC I V I/O REF R I SET COMP O DAC A O DAC C O DAC D O DAC B O SCLOCK I SDATA I/O ALSB ...
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ADV7170/ADV7171 GENERAL DESCRIPTION The ADV7170/ADV7171 is an integrated digital video encoder that converts Digital CCIR-601 4:2 16-bit component video data into a standard analog baseband television signal compatible with worldwide standards. The on-board SSAF (Super Sub-Alias Filter) with ...
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FREQUENCY – MHz Figure 6. NTSC Low-Pass Luma Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 7. PAL Low-Pass ...
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ADV7170/ADV7171 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 12. QCIF Luma Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 13. ...
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FREQUENCY – MHz Figure 18. QCIF Chroma Filter COLOR BAR GENERATION The ADV7170/ADV7171 can be configured to generate 75% amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75% ...
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ADV7170/ADV7171 COMPOSITE VIDEO e.g., VCR OR CABLE H/LTRANSITION COUNT START LOW 128 RESERVED 13 RTC TIME SLOT: 01 ADV7175A/ADV7176A NOTES PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER PLL INCREMENTS ...
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ANALOG VIDEO INPUT PIXELS Y NTSC/PAL M SYSTEM (525 LlNES/60Hz) PAL SYSTEM (625 LINES/50Hz) Mode 0 (CCIR-656): Master Option (Timing Register 0 TR0 = The ADV7170/ADV7171 generates H, V and F signals ...
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ADV7170/ADV7171 DISPLAY 622 623 624 625 H V EVEN FIELD F DISPLAY 309 310 311 312 ODD FIELD ANALOG VIDEO Figure 23. Timing Mode 0 Data Transitions (Master Mode) VERTICAL BLANK ...
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Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7170/ADV7171 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC ...
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ADV7170/ADV7171 Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7170/ADV7171 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input ...
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DISPLAY 622 623 624 625 HSYNC BLANK VSYNC EVEN FIELD DISPLAY 309 310 311 312 HSYNC BLANK VSYNC ODD FIELD Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = ...
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ADV7170/ADV7171 Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7170/ADV7171 accepts or generates Horizontal SYNC ...
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OUTPUT VIDEO TIMING The video timing generator generates the appropriate SYNC, BLANK and BURST sequence that controls the output analog waveforms. These sequences are summarized below. In slave modes, the following sequences are synchronized with the input timing control signals. ...
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ADV7170/ADV7171 The ADV7170/ADV7171 acts as a standard slave device on the bus. The data on the SDATA pin is 8 bits long, supporting the 7-bit addresses, plus the R/W bit. The ADV7170 has 48 subaddresses and the ADV7171 has 26 ...
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SR7 SR6 SR5 SR4 SR7–SR5 (000) ZERO SHOULD BE WRITTEN TO THESE BITS ADV7171 SUBADDRESS REGISTER SR5 SR4 SR3 SR2 SR1 SR0 MODE REGISTER MODE REGISTER 1 ...
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ADV7170/ADV7171 MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4–SR0) = 01H) Figure 39 shows the various operations under the control of Mode Register 1. This register can be read from as well as written to. MR1 BIT DESCRIPTION Interlaced Mode Control ...
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Genlock Control (MR22–MR21) These bits control the genlock feature of the ADV7170/ADV7171. Setting MR21 to a Logic “1” configures the SCRESET/RTC pin as an input. Setting MR22 to Logic Level “0” configures the SCRESET/RTC pin as a subcarrier reset input. ...
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ADV7170/ADV7171 MR46 MR47 SLEEP MODE CONTROL MR46 0 DISABLE 1 ENABLE MR47 (0) ZERO SHOULD BE WRITTEN TO THIS BIT MODE REGISTER 4 MR4 (MR47–MR40) (Address (SR4–SR0) = 04H) Mode Register 8-bit-wide register. Figure 42 shows the ...
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TR0 BIT DESCRIPTION Master/Slave Control (TR00) This bit controls whether the ADV7170/ADV7171 is in master or slave mode. Timing Mode Control (TR02–TR01) These bits control the timing mode of the ADV7170/ADV7171. These modes are described in more detail in the ...
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ADV7170/ADV7171 SUBCARRIER FREQUENCY REGISTER 3–0 (FSC3–FSC0) (Address [SR4–SR0] = 09H–02H) These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following equation –1 Subcarrier Frequency Register = ...
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TC07 TTXREQ RISING EDGE CONTROL TC07 TC06 0 0 " C/W07 WIDE SCREEN SIGNAL CONTROL C/W07 0 DISABLE 1 ENABLE C/W0 BIT DESCRIPTION CGMS Data Bits (C/W03–C/W00) These four data bits are the final four bits of CGMS ...
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ADV7170/ADV7171 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7170/ADV7171 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high ...
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AA 0.1 F 2–9, 12–14 + RESET 100nF “UNUSED INPUTS SHOULD BE + GROUNDED” AA 100k TTX TTXREQ 100k +5V (V TELETEXT PULL-UP AND PULL-DOWN RESISTORS SHOULD ONLY BE ...
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ADV7170/ADV7171 The ADV7170/ADV7171 supports closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. ...
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COPY GENERATION MANAGEMENT SYSTEM (CGMS) The ADV7170/ADV7171 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether ...
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ADV7170/ADV7171 The ADV7170/ADV7171 supports Wide Screen Signalling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7170/ADV7171 is configured in PAL mode. The WSS data is 14 bits long, ...
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ADV7170/ADV7171 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such PD that it appears t = 10.2 s after the leading edge of the horizontal signal. ...
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ADV7170/ADV7171 130.8 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 1067.7mV 286mV (pk-pk) 650mV 232.2mV 0mV 100 IRE 7.5 IRE 0 IRE –40 IRE APPENDIX 6 NTSC WAVEFORMS (WITH PEDESTAL) Figure ...
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IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 1101.6mV 307mV (pk-pk) 650mV 198.4mV 0mV 100 IRE 0 IRE –40 IRE REV. 0 NTSC WAVEFORMS (WITHOUT PEDESTAL) Figure 65. NTSC Composite Video Levels Figure 66. ...
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ADV7170/ADV7171 1284.2mV 1047.1mV 350.7mV 50.8mV 1047mV 350.7mV 50.8mV 1092.5mV 300mV (pk-pk) 650mV 207.5mV 0mV 1050.2mV 351.8mV 51mV PAL WAVEFORMS Figure 69. PAL Composite Video Levels Figure 70. PAL Luma Video Levels 885mV (pk-pk) Figure 71. PAL Chroma Video Levels Figure ...
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BETACAM LEVEL 0mV 171mV 334mV 505mV Figure 73. NTSC 100% Color Bars, No Pedestal U Levels 309mV 158mV BETACAM LEVEL 0mV –158mV –309mV –467mV Figure 74. NTSC 100% Color Bars with Pedestal U Levels 232mV 118mV SMPTE LEVEL ...
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ADV7170/ADV7171 If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7170/ADV7171, the filter shown in Figure 79 can be used. Plots of the filter characteristics are shown in Figure 80, Figure 81 ...
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When external buffering is needed of the ADV7170/ADV7171 DAC outputs, the configuration in Figure 83 is recommended. This configuration shows the DAC outputs running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7170/ADV7171 to ...
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ADV7170/ADV7171 The ADV7170/ADV7171 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite o/p with all DACs powered up ...
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PAL-60 (Continued 4.43361875 MHz) SC Address 14Hex Pedestal Control Register 2 15Hex Pedestal Control Register 3 16Hex CGMS_WSS Reg 0 17Hex CGMS_WSS Reg 1 18Hex CGMS_WSS Reg 2 19Hex TeleText Control Register Power-Up Reset Values NTSC (F = ...
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ADV7170/ADV7171 0.6 0.4 0.2 0.0 0.2 0.0 10.0 NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0. 6.72 s 0.5 0.0 0.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW ...
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L575 10.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW CLAMP TO 0. 6.72 s 100.0 0.5 50.0 0.0 –50.0 0.0 APL = 44.6% 525 LINE NTSC SLOW CLAMP TO 0. 6.72 ...
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ADV7170/ADV7171 0.6 0.4 50.0 0.2 0.0 0.0 –0.2 10.0 NOISE REDUCTION: 15.05dB APL = 44.7% 525 LINE NTSC SLOW CLAMP TO 0. 6.72 s 0.4 50.0 0.2 0.0 –0.2 –50.0 –0.4 0.0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC ...
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APL = 39. SOUND IN SYNC OFF APL = 45.1% YI –Q SETUP 7.5% REV 75% 100 Figure 91. PAL Vector Plot R ...
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ADV7170/ADV7171 COLOR BAR (NTSC) FIELD = 2 LINE = 28 LUMINANCE LEVEL (IRE) 0.4 0.2 30.0 20.0 10.0 0.0 –10.0 CHROMINANCE LEVEL (IRE) 0.0 –0.2 1.0 0.0 –1.0 CHROMINANCE PHASE (DEG –0.1 0.0 –1.0 –2.0 ...
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LUMINANCE NONLINEARITY (NTSC) FIELD = 2 LINE = 21 LUMINANCE NONLINEARITY (%) 99.9 100.4 100.3 100.2 100.1 100.0 99.9 99.8 99.7 99.6 99.5 99.4 99.3 99.2 99.1 99.0 98.9 98.8 98.7 98.6 1ST Figure 95. NTSC Luminance Nonlinearity Measurement CHROMINANCE ...
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ADV7170/ADV7171 NOISE SPECTRUM (NTSC) FIELD = 2 LINE = 64 AMPLITUDE ( 714mV p-p) BANDWIDTH 100kHz TO FULL –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 ...
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PARADE SMPTE/EBU PAL mV Y(A) 700 600 500 400 300 200 100 0 100 200 300 LIGHTNING L183 YI –274.82 0.93% YI 462.80 –0.50% G 307.54 –0.21% R 156.63 –0.22% CY –262.17 –0.13% COLOR Pk-Pk: B-Y 532.33mV Pk-WHITE: 700.4mV (100%) ...
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ADV7170/ADV7171 COMPONENT NOISE LINE = 202 AMPLITUDE (0dB = 700mV p-p) BANDWIDTH 10kHz TO 5.0MHz 0.0 –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 COMPONENT MULTIBURST LINE = ...
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GREEN (A) 700 600 500 400 300 200 100 0 100 200 300 REV. 0 COMPONENT VECTOR SMPTE/EBU, 75 Figure 103. PAL YUV Vector Plot mV BLUE (B) 700 600 500 400 300 200 ...
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ADV7170/ADV7171 INDEX Contents FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Quad Flatpack (PQFP) (S-44) 0.548 (13.925) 0.546 (13.875) 0.096 (2.44) 0.398 (10.11) MAX 0.390 (9.91) 0.037 (0.94) 8 0.025 (0.64) 33 0.8 34 SEATING PLANE TOP VIEW (PINS ...