ADV7170SU AD [Analog Devices], ADV7170SU Datasheet - Page 24

• Manufacturer Part Number: ADV7170SU
• Manufacturer: AD [Analog Devices]

ADV7170/ADV7171
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 39 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)
This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
Closed Captioning Field Control (MR12–MR11)
These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
DAC Control (MR16–MR13)
These bits can be used to power down the DACs. This can
be used to reduce the power consumption of the ADV7170/
ADV7171 if any of the DACs are not required in the application.
ALL ZEROS INVALID
MR37
0
1
CONTROL
MR17
0
1
COLOR BAR
CONTROL
DISABLE
ENABLE
RESERVED
MR37
MR27
MR27
DISABLE
ENABLE
MR36
TTX BIT REQUEST
MODE CONTROL
MR17
0
1
LOW POWER MODE
MR26
MR16
0
1
0
1
NORMAL
BIT REQUEST
MR36
CONTROL
SELECT
NORMAL
POWER-DOWN
DAC A
DISABLE
ENABLE
MR26
MR16
MR25
MR35
0
1
0
1
MR15
TELETEXT
CONTROL
0
1
MR35
ENABLE BURST
DISABLE BURST
CONTROL
DISABLE
ENABLE
CONTROL
BURST
NORMAL
POWER-DOWN
MR25
DAC B
MR15
CHROMA OUTPUT
MR34
MR24
Figure 39. Mode Register 1
Figure 40. Mode Register 2
Figure 41. Mode Register 3
0
1
0
1
MR14
CHROMINANCE
SELECT
0
1
MR34
CONTROL
ENABLE COLOR
DISABLE COLOR
DISABLE
ENABLE
CONTROL
MR33
MR24
NORMAL
POWER-DOWN
DAC D
MR14
0
1
MR23
ACTIVE VIDEO LINE WIDTH
COMPOSITE
GREEN/LUMA/Y
0
1
MR13
–24–
MR33
0
1
DAC A
MR23
CONTROL
MR13
CONTROL
Color Bar Control (MR17)
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 75/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7170/ADV7171 is config-
ured in a master timing mode.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4-SR0] = 02H)
Mode Register 2 is an 8-bit-wide register.
Figure 40 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
MR2 BIT DESCRIPTION
Square Pixel Mode Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied.
NORMAL
POWER-DOWN
CCI R624 OUTPUT
CCI R601 OUTPUT
MR32
DAC C
0
1
VBI_OPEN
MR22 MR21
MR32
x
0
1
MR12 MR11
DISABLE
ENABLE
0
0
1
1
BLUE/COMP/U
BLUE/COMP/U
GENLOCK SELECTION
MR12
MR22
DAC OUTPUT
CLOSED CAPTIONING
0
1
1
SWITCHING
DAC B
FIELD SELECTION
0
1
0
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
MR31
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
MR11
MR21
RED/CHROMA/V
RED/CHROMA/V
RESERVED
MR10
0
1
MR30
MR30
MR31
DAC C
MR20
SQUARE PIXEL
0
1
INTERLACED
NONINTERLACED
INTERLACE
MR10
MR20
CONTROL
CONTROL
DISABLE
ENABLE
GREEN/LUMA/Y
COMPOSITE
DAC D
REV. 0