ADV7170SU AD [Analog Devices], ADV7170SU Datasheet - Page 14

• Manufacturer Part Number: ADV7170SU
• Manufacturer: AD [Analog Devices]

ADV7170/ADV7171
Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre-/post-equalization
pulses (see Figures 21 to 32). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
The complete VBI is comprised of the following lines:
525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335.
The “Opened VBI” consists of:
525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2.
625/50 Systems, Line 7 to Line 22 and Lines 319 to 335.
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7170/ADV7171 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC and BLANK
(if not used) pins should be tied high during this mode.
RTC
NOTES:
1
2
3
F
SEQUENCE BIT
RESET BIT
F
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
RESET ADV7175A/ADV7176A’s DDS
BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171.
SC
SC
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
H/LTRANSITION
COUNT START
TIME SLOT: 01
128
COMPOSITE
LOW
OR CABLE
e.g., VCR
13
VIDEO
ADV7175A/ADV7176A
RESERVED
14 BITS
NOT USED IN
(e.g., ADV7185)
Figure 19. RTC Timing and Connections
DECODER
DECODER
MPEG
VIDEO
0
14
RESERVED
4 BITS
19
21
M
U
X
–14–
CLOCK
SCRESET/RTC
HSYNC
FIELD/VSYNC
P7–P0
ADV7170/ADV7171
SAMPLE
FSCPLL INCREMENT
VALID
BLUE/COMPOSITE/U
RED/CHROMA/V
GREEN/LUMA/Y
SAMPLE
INVALID
COMPOSITE
1
RESERVED
5 BITS
8/LLC
0
SEQUENCE
BIT
2
67 68
RESET
BIT
3
RESERVED
REV. 0