ADV7170SU AD [Analog Devices], ADV7170SU Datasheet - Page 19

• Manufacturer Part Number: ADV7170SU
• Manufacturer: AD [Analog Devices]

Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illus-
trates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 30 illustrates the
HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
REV. 0
VSYNC
HSYNC
HSYNC
VSYNC
BLANK
BLANK
622
309
HSYNC
BLANK
VSYNC
HSYNC
BLANK
PIXEL
DATA
VSYNC
DISPLAY
DISPLAY
PIXEL
DATA
623
310
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
624
311
EVEN FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
ODD FIELD
625
312
313
1
Figure 28. Timing Mode 2 (PAL)
314
2
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
315
3
ODD FIELD
VERTICAL BLANK
VERTICAL BLANK
EVEN FIELD
–19–
316
4
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
317
5
Cb
318
6
Y
319
7
Cr
320
Y
Cb
Cb
21
ADV7170/ADV7171
Y
334
22
Cr
DISPLAY
335
23
Y
DISPLAY
336