adv7152 Analog Devices, Inc., adv7152 Datasheet - Page 12

• Manufacturer Part Number: adv7152
• Description: Cmos 220 Mhz True-color Graphics Triple 10-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

ADV7152
Alternatively, the ADV7152 CLOCK inputs can be driven by a
Programmable Clock Generator (Figure 13), such as the
ICS1562. The ICS1562 is a monolithic, phase-locked-loop,
clock generator chip. It is capable of synthesizing differential
ECL output frequencies in a range up to 220 MHz from a single
low frequency reference crystal.
Figure 13. PLL Generator Driving CLOCK, CLOCK of the
ADV7152
CLOCK CONTROL SIGNALS LOADOUT
The ADV7152 generates a LOADOUT control signal which
runs at a divided down frequency of the pixel CLOCK. The
frequency is automatically set to the programmed multiplex
rate, controlled by CR36 of Command Register 3.
f
f
The LOADOUT signal is used to directly drive the LOADIN
pixel latch signal of the ADV7152. This is most simply achieved
by tying the LOADOUT and LOADIN pins together. Alterna-
tively, the LOADOUT signal can be used to drive the frame
buffer’s shift clock signals, returning to the LOADIN input de-
layed with respect to LOADOUT.
Figure 14. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK )
LOADOUT
LOADOUT
LOADOUT
LOW FREQUENCY
BUFFER
V
FRAME
LOADIN
VIDEO
CLOCK
OSCILLATOR
= f
= f
D0–D3 CS R/W
+5V
GENERATOR
CLOCK
CLOCK
CLOCK
GND
V
ECL
ECL
REF
/2
OUT–
OUT+
OUT
LOADOUT
ADV7152
LOADIN
PIXEL
DATA
2:1 Multiplex Mode
1:1 Multiplex Mode
GND
GND
V
CC
330
220
LOADOUT(2)
LOADOUT(1)
BUFFER
FRAME
VIDEO
GND
V
CC
0.1 F
330
220
LOADOUT(1)
LOADOUT(2)
V
AA
CLOCK
CLOCK
V
ADV7152
REF
DELAY
LOADOUT
ADV7152
LOADIN
PIXEL
DATA
GND
V
+5V
AA
–12–
If it is not necessary to have a known fixed number of pipeline
delays, then there is no limitation on the delay between LOAD-
OUT and LOADIN (LOADOUT(1) and LOADOUT(2)).
LOADIN and Pixel Data must conform to the setup and hold
times (t
If however, it is required that the ADV7152 has a fixed number
of pipeline delays (t
form to timing specifications t
ures 4 and 5.
PRGCKOUT
The PRGCKOUT control signal outputs a user programmable
clock frequency. It is a divided down frequency of the pixel
CLOCK (see Figure 8). The rising edge of PRGCKOUT is
synchronous to the rising edge of LOADOUT
where N = 4, 8, 16 or 32.
One application of the PRGCKOUT is to use it as the master
clock frequency of the graphics subsystems processor or
controller.
SCKIN, SCKOUT
These video memory signals are used to minimize external sup-
port chips. Figure 15 illustrates the function that is provided.
An input signal applied to SCKIN is synchronously AND-ed
with the video blanking signal (BLANK). The resulting signal is
output on SCKOUT. Figure 7 of the Timing Waveform section
shows the relationship between SCKOUT, SCKIN and
BLANK.
The SCKOUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 16
shows a suggested frame buffer to ADV7152 interface. This is a
minimum chip solution and allows the ADV7152 control the
overall graphics system clocking and synchronization.
Figure 16. ADV7152 Interface Using SCKIN and SCKOUT
8
and t
SCKOUT
Figure 15. SCKOUT Generation Circuit
BLANK
SCKIN
SYNC
9
).
BUFFER
FRAME
VIDEO
PD
f
), LOADOUT and LOADIN must con-
PRGCKOUT
10
= f
and -t
CLOCK
LOADOUT
LOADIN
SCKIN
BLANK
SCKOUT
PIXEL
DATA
11
ADV7152
/N
as illustrated in Fig-
LATCH
ENABLE
REV. B