ad1986ajcpz-reel Analog Devices, Inc., ad1986ajcpz-reel Datasheet - Page 33
ad1986ajcpz-reel
Manufacturer Part Number
ad1986ajcpz-reel
Description
Ac ?97 And Hd Audio Soundmax Codec
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD1986AJCPZ-REEL.pdf
(56 pages)
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Register
(SPDIF
Configuration
Valid)
PRI
(Center DAC
Power-Down)
PRJ
(Surround
DACs Power-
Down)
PRK
(LFE DAC
Power-Down)
x
FRONT DAC PCM RATE (REGISTER 0x2C)
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit
(0x2A D00) is 0 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register can be programmed with the actual sample rate.
To use 96 kHz in AC ’97 mode set the double rate audio (DRA) bit (0x2A D01). When using DRA in AC ’97, only the front DACs are
supported and all other DACs (surround, center, and LFE) are automatically powered down.
Reg
0x2C
Table 92.
Register
R [15:0]
(Sample
Rate)
Name
Front DAC PCM
Rate
Function
The sampling frequency range is from 7 kHz (0x01B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to VRA, then the
sample rates are reset to 48 kHz.
Function
SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status.
SPCV
0
1
Actual status reflected in the CDAC (0x3A D06) bit.
PRI
0
1
Actual status reflected in the SDAC bit.
PRJ
0
1
Actual status reflected in the LDAC bit.
PRK
0
1
Reserved.
D15
R15
D14
R14
S/PDIF Configuration Status
Invalid SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS)
Valid SPDIF configuration
CENTER DAC Power Status
Power on center DAC
Power down center DAC
Surround DACs Power Control
Power on surround DACs
Power down surround DACs
LFE DACs Power Control
Power on LFE DAC
Power down LFE DAC
D13
R13
D12
R12
D11
R11
Rev. 0 | Page 33 of 56
D10
R10
D9
R9
D8
R8
D7
R7
D6
R6
D5
R5
R4
D4
D3
R3
D2
R2
D1
R1
Default
Default
Default
Default: 0
R0
D0
AD1986A
Default
0xBB80
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