ad394td/883b Analog Devices, Inc., ad394td/883b Datasheet - Page 7

• Manufacturer Part Number: ad394td/883b
• Description: Dac 4-ch 12-bit 28-pin Cdip
• Manufacturer: Analog Devices, Inc.

THEORY OF OPERATION
The AD394 quad DAC provides four-quadrant multiplication.
It is a hybrid IC comprised of four, monolithic, 12-bit, CMOS,
multiplying DACs and eight precision output amplifiers. Each
of the four independent-buffered channels has an independent
reference input capable of accepting a separate dc or ac signal
for multiplying or for function generation applications. The
CMOS DACs act as digitally programmable attenuators when
used with a varying input signal or, if used with a fixed dc
reference, the DAC would act as a standard bipolar output DAC.
In addition, each DAC has a 12-bit wide data latch to buffer the
converter when connected to a microprocessor data bus.
MULTIPLYING MODE
Figure 5 shows the transfer function. The diagram indicates an
area over which many different combinations of the reference
input and digital input can result in a particular analog output
voltage. The highlighted transfer line in the diagram indicates
the transfer function if a fixed reference is at the input. The
digital code above the diagram indicates the midpoint and
endpoints of each function. The relationship between the
reference input (V
output is given in Table 4. Note that the reference input signal
sets the slope of the transfer function (and determines the full-
scale output at code 111...111), while the digital input selects the
horizontal position in each diagram.
Table 4. Bipolar Code Table
Data Input
1111
1100
1000
1000
0111
0100
0000
1111
0000
0000
0000
1111
0000
0000
REFIN
), the digital input code, and the analog
1111
0000
0001
0000
1111
0000
0000
Analog Output
1 × (V
1 × (V
1 × (V
1 × (V
−1 × (V
−1 × (V
−1 × (V
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
)
)
)
)
)
)
)
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2047
2048
1024
2048
2048
2048
2048
1024
2048
2048
2048
1
1
0
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DATA AND CONTROL SIGNAL FORMAT
The AD394 accepts 12-bit parallel data in response to Control
Signals CS1 – CS4 . As detailed in Table 3, the four chip select
lines are used to address the DAC register of interest. It is per-
missible to have more than one chip select active at any time. If
CS1 – CS4 are all brought low coincident, all four DAC outputs
will be updated to the value located on the data bus. All control
inputs are level-triggered and may be hard-wired low to render
any register (or group of registers) transparent.
Table 3. DAC Select Matrix
CS1
1
0
1
1
1
0
CS2
1
1
0
1
1
0
Figure 5. The AD394 as a Four-Quadrant Multiplier
Analog Output Voltage, V
9.9951 V
5.000 V
4.88 mV
0.000 V
−4.88 mV
−5.000 V
−10.000 V
CS3
1
1
1
0
1
0
of Reference and Digital Input
CS4
1
1
1
1
0
0
Operation
All DACs latched
Load DAC 1 from data bus
Load DAC 2 from data bus
Load DAC 3 from data bus
Load DAC 4 from data bus
All DACs simultaneously loaded
Full Scale − 1 LSB
1/2 Scale
1 LSB
Zero
−1LSB
−1/2 Scale
−Full Scale
REFIN
= 10 V
AD394