atf280e ATMEL Corporation, atf280e Datasheet
atf280e
Related parts for atf280e
atf280e Summary of contents
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... Ceramic packages – 256pins MQFPF (150 I/Os, 8 LVDS Tx and 8 LVDS Rx) – 472pins MCGA (308 I/Os, 8 LVDS Tx and 8 LVDS Rx) • Design Kit including – ATF280E and Configurator Samples – Evaluation Board – Software Design Tools – ISP Cable/Dongle TM , DFF, JTAG, I/O buffers) Rad Hard ...
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... LVDS Transmit channels, 8 LVDS Receive channels and a complete set of cold sparing programmable I/Os. The ATF280E I/Os are fully PCI-compliant. The ATF280E is available in two space qualified packages. The MCGA472 package offers up to 324 I/Os for user application. The MQFP256 package is also proposed for application requiring less than 166 I/Os. ...
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... OLVDS5 11 B12 ILVDS6N 11 B13 ILVDS6 11 B14 IO 10 B15 IO/CS0 10 B16 VCC 10 B17 IO 10 B18 IO 10 B19 IO 10 7750A–AERO–07/07 ATF280E MCGA472 pin assignment LEAD Signal Cluster C7 IO/ IO/CHECKN C10 OLVDS6N 11 C11 OLVDS6 11 C12 ILVDS5N 11 C13 ILVDS5 11 C14 IO 10 ...
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... LEAD Signal Cluster B20 VDD 4 B21 VSS 3 C1 VDD 4 C2 VDD 4 C3 VSS ATF280E 4 LEAD Signal Cluster D21 VCC 9 D22 VSS 6 E1 VCC VCC 12 LEAD Signal F21 IO/D9 F22 IO G1 ...
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... H15 VCC 10 H16 VCC 9 H17 IO 9 H18 IO 9 H19 IO 9 H20 IO 9 H21 IO 9 H22 IO 9 7750A–AERO–07/07 ATF280E MCGA472 pin assignment LEAD Signal Cluster J8 VCC J10 IO 12 J11 IO 12 J12 IO 12 J13 IO 10 J14 IO/GCK5 10 J15 VCC ...
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... LEAD Signal Cluster IO/ VCC ATF280E 6 LEAD Signal Cluster L2 ILVDS8N 2 L3 ILVDS7N 2 L4 VCC 1 L5 REFNorth IO/A8 3 LEAD Signal Cluster N3 OLVDS8N IO/ VCC 3 N8 IO/A12 3 N9 ...
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... IO P13 IO P14 IO/GCK3 P15 VCC P16 IO P17 VCC P18 IO P19 IO P20 IO P21 IO P22 7750A–AERO–07/07 ATF280E MCGA472 pin assignment LEAD Signal 4 R10 IO 4 R11 VCCB 6 R12 VCC 7 R13 IO 7 R14 VCC 7 R15 VCC 7 R16 IO 7 R17 IO 7 R18 ...
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... LEAD Signal Cluster IO/A10 VCC R8 VCC R9 VCC ATF280E 8 LEAD Signal 3 U4 TDI 3 U5 VCC 3 U6 IO/GCK8/A15 3 U7 TRST VCC Cluster LEAD Signal 3 W4 VCC 7750A–AERO–07/07 Cluster ...
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... OLVDS2 Y13 OLVDS2N Y14 IO Y15 IO Y16 IO Y17 VCC Y18 IO Y19 IO/OTSN Y20 VSS Y21 VDD Y22 VDD AA2 VSS AA3 VDD 7750A–AERO–07/07 ATF280E MCGA472 pin assignment Cluster LEAD 4 AA4 4 AA5 6 AA6 6 AA7 6 AA8 6 AA9 6 AA10 6 AA11 6 AA12 6 AA13 7 AA14 7 ...
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... RESETn is the FPGA configuration manual reset pin available during all configuration states. It initiates a configuration clear cycle and, if operating in Mode 0, an auto configuration dedicated Schmitt trigger input with approximately 1V of hysteresis for noise immunity pulled to VCC with a nominal 50K internal resistor. INIT - (Input/Output) ATF280E 10 7750A–AERO–07/07 ...
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... D1:D15 - Configuration Data Bus - Upper bits (Input/Output) D1:D15 are the upper bits of the 8/16-bit parallel data bus used to download configuration data to the device. During power-on-reset or manual reset, D1:D15 are controlled by the configura- 7750A–AERO–07/07 ATF280E 11 ...
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... CHECK is a configuration control pin used to control the Check Function. The Check Function takes a bitstream and compares it to the contents of a previously loaded bitstream and notifies the user of any differences. Any differences causes the INIT pin to go Low. During power-on- ATF280E 12 7750A–AERO–07/07 ...
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... Power Supply VDD - Core Power Supply VDD is the power supply input for the ATF280E core. VDD = 1.8V ± 0.2V VCCy - I/O Power Supply VCC is the power supply input for the programmable I/Os. Each I/O cluster has dedicated VCCy sources where ‘y’ is the cluster number (1 < y < 8). VCC can be independently configured to either 1.8V ± ...
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... The Symmetrical Array At the heart of the Atmel ATF280E architecture is a symmetrical array of identical cells. The array is continuous from one edge to the other, except for bus repeaters spaced every four cells. At the intersection of each repeater row and column RAM block accessible by adja- cent buses ...
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... Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. This is done automatically using the integrated development system (IDS) tool. ATF280E ( ...
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... The Core Cell The following figure depicts the ATF280E cell which is a highly configurable logic block based around two 3-input LUTs ( ROM), and which can be combined to produce one 4-input LUT. This means that any cell can implement two functions of 3 inputs or one function of 4 inputs. ...
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... Arithmetic Mode This mode is frequently used in many designs. As can be seen in the figure, the ATF280E core cell can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core cell. Note that the sum output in this diagram is registered. This output could then be tri-stated and/or fed back into the cell ...
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... Tri-state/Mux Mode This mode is used in many telecommunications applications, where data needs to be routed through more than one possible path. The output of the core cell is very often tri-statable for many inputs to many outputs data switching. Figure 4-8. ATF280E 18 ounter Mode C Tri-state/Mux Mode 7750A–AERO–07/07 ...
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... Each local-bus segment spans four cells and connects to consecutive repeaters. Each express- bus segment spans eight cells and “leapfrogs” or bypasses a repeater. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. 7750A–AERO–07/07 Busing Plane ATF280E 19 ...
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... Express/Express turns are implemented through separate pass gates distributed throughout the array. 4.3.1 Dual Function Bus Resource Some of the bus resource on the ATF280E are used as a dual-function resource. The table hereafter shows which buses are used in a dual-function mode and which bus plane is used. Table 4-1. Function ...
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... The following figure presents the direct connections between a cell and its eight nearest neigh- bors. It also summarizes the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing plane). Figure 4-10. Cell Connections 7750A–AERO–07/07 ATF280E 21 ...
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... TM 5. FreeRAM The ATF280E offers 115Kbits of dual-port RAM called FreeRAM dual-ported RAM blocks and dispersed throughout the array as shown in the figure here- after. This FreeRAM A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed over four sector rows (plane 2) ...
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... Figure 5-2. Note: Here is an example of a RAM macro constructed using ATF280E’s FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchronous RAM. Note the very small amount of external logic required to complete the address decoding for the macro. Most of the logic cells in the sectors 7750A– ...
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... RAM will be unused: they can be used for other logic in the design. This logic can be automatically generated using the macro generators. Figure 5-3. ATF280E 24 RAM Example: 128 x 8 Dual-ported RAM (Asynchronous) 7750A–AERO–07/07 ...
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... Clocking Scheme The entire ATF280E clocking scheme (including clock trees and muxes) is SET hardened. There are eight differential Global Clock buses (GCK1 - GCK8) on the ATF280E FPGA. In addi- tion to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4). Each column of an array has a “Column Clock mux” and a “Sector Clock mux”. The Column Clock mux is at the top of every column of an array and the Sector Clock mux is at every four cells ...
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... Fast Clocks There are four Fast Clocks (FCK1 - FCK4) on the ATF280E, two per edge column of the array for PCI specification. Even the derived clocks can be routed through the Global network. Access points are provided in the corners of the array to route the derived clocks into the global clock network ...
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... Set/Reset Scheme The ATF280E reset scheme is essentially the same as the clock scheme except that there is only one differential Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks). Like the clocking scheme, set/reset scheme is SET hardened ...
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... Figure 7-1. ATF280E 28 Set/Reset (for One Column of Cells) 7750A–AERO–07/07 ...
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... Schmitt trigger can be enabled on the I/O. When configured as output optional PCI compatibility can be enabled. In addition it is possible to select the buffer drive to optimize speed of the application. In addition, the ATF280E provides pull-up and pull-down capability on each I/O. The following section presents all the configuration available on the programmable I/Os 8.1.1 Pull-up/Pull-down Each pad has a programmable pull-up and pull-down attached to it. This supplies a weak “ ...
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... Dual-use pins share input buffers. It should be noted that even when the configuration has claimed a pin for its own purposes, the user input buffer is still fully functional. This implies that any user logic tied to the input buffers of the pins in question will remain operational. ATF280E 30 Drive Capability for VCC = 3.3V VCC = 3 ...
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... The LVDS specification complies with the EIA-644 standard requirements. 8.2.1 JTAG All LVDS I/Os are 1149.1 compliant. Each I/O may be included or excluded from boundary scan chain during the configuration of the FPGA. 7750A–AERO–07/07 Dual Use I/O principle ATF280E 31 ...
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... ATF280E Configuration Configuration is the process by which a design is loaded into an ATF280E FPGA. The ATF280E device is a SRAM based FPGA. this lead to an unlimited reprogrammability capability possible to configure either the entire device or only a portions of the device. Sections can be configured while others continue to operate undisturbed. The architecture of the ATF280E leads to a maximum bitstream size of 3M bits ...
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... Figure 9-1. For complete description of all the ATF280E configuration modes please refer to the “AT40K Series Configuration” application note on the ATMEL web site www.atmel.com. 9.3 Configuration Check The download of the bit-stream from the EEPROM to the FPGA is checked (CRC). Once config- ured the FPGA will also self check the integrity of the configuration and generate a warning as soon as a difference is detected. 7750A– ...
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... Development Software The ATF280E is designed to quickly implement high performance, large gate count designs through the use of combined Atmel and industry standard tools used on Windows/Linux platform. ATF280E 34 7750A–AERO–07/07 ...
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... Devices are guaranteed to initialize properly at 50% of the minimum current listed above. A larger capacity power supply may result in a larger initialization current Ramp-up time is measured from 1.8V DC. Peak current required lasts less than 2 ms, and occurs near the internal power on reset threshold voltage. ATF280E Maximum Current(1)( ...
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... Operating Range Table 12-1. Operating Temperature VCC - I/O Power Supply VCCB - LVDS I/O Power Supply VREF - LVDS Reference Voltage VDD - Core Power Supply ATF280E 36 (1) *NOTICE: Operating Range Stresses at or above those listed under "Abso- lute Maximum Ratings” may cause permanent damage to the device. This is a stress rating ...
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... OUT CC Without pull-up OUT SS With pull-up for CON OUT SS Standby, un-programmed All pins Vdd = Vss = 0V Vin = 0 to VDD Max Vdd = Vss = 0V Vin = 0 to VDD Max Iocs = 100 µA ATF280E Min Typ Max Units 70 -0.3 30 2.4 V 2.4 V 2 ...
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... Tp Propagation delay Tsk1 Duty cycle skew Channel to channel skew Tsk2 (same edge) Figure 12-1. Test Termination Measurements Figure 12-2. Rise and Fall times Measurements ATF280E 38 LVDS Driver DC/ AC Characteristics Test Condition Min. Rload = 100Ω 251.4 Rload = 100Ω 1071 Rload = 100Ω ...
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... Units Notes ns rising edge clock ns rising edge clock ns rising edge clock ns rising edge clock ns from any pad to Global Set/Reset network ATF280E Comments – – – – to the pad ...
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... CD Read t (Maximum) AD Read t (Maximum) OZX Read t (Maximum) OXZ Notes: ATF280E 40 Path Value clock pad -> out clock pad -> out FreeRAM AC Characteristics cycle time addr setup -> addr hold -> we din setup -> we din hold -> we din -> dout rd addr -> dout oe -> dout oe -> ...
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... FreeRAM Asynchronous Timing Characteristics 12.4.1 12.4.1.1 Single-port Write/Read 12.4.1.2 Dual-port Write with Read Dual-port Read 12.4.1.3 7750A–AERO–07/07 ATF280E 41 ...
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... FreeRAM Synchronous Timing Characteristics 12.4.2.1 Single-port Write/Read 12.4.2.2 Dual-port Write with Read 12.4.2.3 Dual-port Read ATF280E 42 7750A–AERO–07/07 ...
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... Packaging Information MCGA 472 7750A–AERO–07/07 ATF280E 43 ...
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... MQFPT ATF280E 44 7750A–AERO–07/07 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. ©2007 Atmel Corporation. All rights reserved. Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. ...